diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/Makefile cset-v2.4.20/arch/ppc/Makefile --- cset-v2.4.20~/arch/ppc/Makefile 2004-10-25 14:59:26.000000000 +0900 +++ cset-v2.4.20/arch/ppc/Makefile 2004-11-01 22:35:08.000000000 +0900 @@ -17,10 +17,6 @@ # Be sure to change PAGE_OFFSET in include/asm-ppc/page.h to match KERNELLOAD =0xc0000000 -ifeq ($(shell uname -m),ppc) -CHECKS = checks -endif - LINKFLAGS = -T arch/ppc/vmlinux.lds -Ttext $(KERNELLOAD) -Bstatic CPPFLAGS := $(CPPFLAGS) -I$(TOPDIR)/arch/$(ARCH) AFLAGS := $(AFLAGS) -I$(TOPDIR)/arch/$(ARCH) @@ -47,18 +43,13 @@ CFLAGS += $(shell echo $(CONFIG_COMPILE_OPTIONS) | sed -e 's/"//g') endif -ifdef CONFIG_4xx - HEAD := arch/ppc/kernel/head_4xx.o -else - ifdef CONFIG_8xx - HEAD := arch/ppc/kernel/head_8xx.o - else - HEAD := arch/ppc/kernel/head.o - ifdef CONFIG_6xx - HEAD += arch/ppc/kernel/idle_6xx.o - endif - endif -endif +HEAD-y := arch/ppc/kernel/head.o +HEAD-$(CONFIG_40x) := arch/ppc/kernel/head_4xx.o +HEAD-$(CONFIG_44x) := arch/ppc/kernel/head_44x.o +HEAD-$(CONFIG_8xx) := arch/ppc/kernel/head_8xx.o +HEAD-$(CONFIG_6xx) += arch/ppc/kernel/idle_6xx.o + +HEAD := $(HEAD-y) ARCH_SUBDIRS = arch/ppc/kernel arch/ppc/platforms arch/ppc/mm arch/ppc/lib SUBDIRS := $(SUBDIRS) $(ARCH_SUBDIRS) @@ -100,7 +91,7 @@ # All the instructions talk about "make bzImage". bzImage: zImage -$(BOOT_TARGETS): $(CHECKS) vmlinux +$(BOOT_TARGETS): vmlinux @$(MAKEBOOT) $@ %_config: arch/ppc/configs/%_defconfig diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/boot/common/misc-simple.c cset-v2.4.20/arch/ppc/boot/common/misc-simple.c --- cset-v2.4.20~/arch/ppc/boot/common/misc-simple.c 2004-10-25 15:05:51.000000000 +0900 +++ cset-v2.4.20/arch/ppc/boot/common/misc-simple.c 2004-11-02 17:38:17.000000000 +0900 @@ -44,6 +44,12 @@ #define HAS_KEYB 0 #endif +/* Will / Can the user give input? */ +#if (defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_VGA_CONSOLE)) \ + && !defined(CONFIG_GEMINI) +#define INTERACTIVE_CONSOLE 1 +#endif + char *avail_ram; char *end_avail; char *zimage_start; @@ -148,8 +154,7 @@ memcpy (cmd_line, cmd_preset, sizeof(cmd_preset)); while ( *cp ) putc(*cp++); -#if (defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_VGA_CONSOLE)) \ - && !defined(CONFIG_GEMINI) +#ifdef INTERACTIVE_CONSOLE /* * If they have a console, allow them to edit the command line. * Otherwise, don't bother wasting the five seconds. diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/boot/common/ns16550.c cset-v2.4.20/arch/ppc/boot/common/ns16550.c --- cset-v2.4.20~/arch/ppc/boot/common/ns16550.c 2004-10-25 15:03:48.000000000 +0900 +++ cset-v2.4.20/arch/ppc/boot/common/ns16550.c 2004-11-01 22:35:08.000000000 +0900 @@ -98,8 +98,3 @@ { return ((inb(com_port + (UART_LSR << shift)) & UART_LSR_DR) != 0); } - -void -serial_close(unsigned long com_port) -{ -} diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/boot/common/serial_stub.c cset-v2.4.20/arch/ppc/boot/common/serial_stub.c --- cset-v2.4.20~/arch/ppc/boot/common/serial_stub.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/boot/common/serial_stub.c 2004-11-01 22:35:08.000000000 +0900 @@ -0,0 +1,28 @@ +/* + * arch/ppc/boot/common/serial_stub.c + * + * This is a few stub routines to make the boot code cleaner looking when + * there is no serial port support doesn't need to be closed, for example. + * + * Author: Tom Rini + * + * 2003 (c) MontaVista, Software, Inc. This file is licensed under the terms + * of the GNU General Public License version 2. This program is licensed "as + * is" without any warranty of any kind, whether express or implied. + */ + +void __attribute__ ((weak)) +serial_fixups(void) +{ +} + +unsigned long __attribute__ ((weak)) +serial_init(int chan, void *ignored) +{ + return 0; +} + +void __attribute__ ((weak)) +serial_close(unsigned long com_port) +{ +} バイナリー・ファイルcset-v2.4.20~/arch/ppc/boot/images/vmlinux.gzとcset-v2.4.20/arch/ppc/boot/images/vmlinux.gzは違います バイナリー・ファイルcset-v2.4.20~/arch/ppc/boot/images/zImage.ocoteaとcset-v2.4.20/arch/ppc/boot/images/zImage.ocoteaは違います diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/boot/prep/Makefile cset-v2.4.20/arch/ppc/boot/prep/Makefile --- cset-v2.4.20~/arch/ppc/boot/prep/Makefile 2004-10-25 15:06:05.000000000 +0900 +++ cset-v2.4.20/arch/ppc/boot/prep/Makefile 2004-11-01 22:35:08.000000000 +0900 @@ -25,7 +25,8 @@ LD_ARGS = -T ../ld.script -Ttext 0x00800000 -Bstatic obj-y := head.o ../simple/legacy.o misc.o of1275.o \ ../common/util.o ../common/string.o \ - ../common/misc-common.o + ../common/misc-common.o \ + ../common/serial_stub.o OBJCOPY_ARGS = -O elf32-powerpc LIBS = ../lib/zlib.a diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/boot/prep/misc.c cset-v2.4.20/arch/ppc/boot/prep/misc.c --- cset-v2.4.20~/arch/ppc/boot/prep/misc.c 2004-10-25 15:00:04.000000000 +0900 +++ cset-v2.4.20/arch/ppc/boot/prep/misc.c 2004-11-01 22:35:08.000000000 +0900 @@ -23,6 +23,16 @@ #include "nonstdio.h" #include "zlib.h" +#ifdef CONFIG_CMDLINE +#define CMDLINE CONFIG_CMDLINE +#else +#define CMDLINE "" +#endif + +#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_VGA_CONSOLE) +#define INTERACTIVE_CONSOLE 1 +#endif + /* * Please send me load/board info and such data for hardware not * listed here so I can keep track since things are getting tricky @@ -38,11 +48,6 @@ extern char __ramdisk_begin, __ramdisk_end; extern char _end[]; -#ifdef CONFIG_CMDLINE -#define CMDLINE CONFIG_CMDLINE -#else -#define CMDLINE "" -#endif char cmd_preset[] = CMDLINE; char cmd_buf[256]; char *cmd_line = cmd_buf; @@ -56,9 +61,7 @@ char *zimage_start; int zimage_size; -#if defined(CONFIG_SERIAL_CONSOLE) unsigned long com_port; -#endif /* CONFIG_SERIAL_CONSOLE */ #ifdef CONFIG_VGA_CONSOLE char *vidmem = (char *)0xC00B8000; int lines = 25, cols = 80; @@ -122,9 +125,12 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum, RESIDUAL *residual, void *OFW_interface) { +#ifdef INTERACTIVE_CONSOLE int timer = 0; + char ch; +#endif extern unsigned long start; - char *cp, ch; + char *cp; unsigned long TotalMemory; int dev_handle; int mem_info[2]; @@ -135,9 +141,7 @@ unsigned int pci_viddid, pci_did, tulip_pci_base, tulip_base; serial_fixups(); -#if defined(CONFIG_SERIAL_CONSOLE) com_port = serial_init(0, NULL); -#endif /* CONFIG_SERIAL_CONSOLE */ #if defined(CONFIG_VGA_CONSOLE) vga_init((unsigned char *)0xC0000000); #endif /* CONFIG_VGA_CONSOLE */ @@ -304,6 +308,11 @@ memcpy (cmd_line, cmd_preset, sizeof(cmd_preset)); while ( *cp ) putc(*cp++); +#ifdef INTERACTIVE_CONSOLE + /* + * If they have a console, allow them to edit the command line. + * Otherwise, don't bother wasting the five seconds. + */ while (timer++ < 5*1000) { if (tstc()) { while ((ch = getc()) != '\n' && ch != '\r') { @@ -328,6 +337,7 @@ } udelay(1000); /* 1 msec */ } +#endif *cp = 0; puts("\nUncompressing Linux..."); diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/boot/simple/Makefile cset-v2.4.20/arch/ppc/boot/simple/Makefile --- cset-v2.4.20~/arch/ppc/boot/simple/Makefile 2004-10-25 14:58:52.000000000 +0900 +++ cset-v2.4.20/arch/ppc/boot/simple/Makefile 2004-11-01 22:35:08.000000000 +0900 @@ -30,22 +30,35 @@ TFTPIMAGE := /tftpboot/zImage.embedded MISC := misc-embedded.o endif +ifeq ($(CONFIG_EBONY),y) +ZIMAGE := zImage-TREE +ZIMAGEINITRD := zImage.initrd-TREE +END := ebony +ENTRYPOINT := 0x00800000 +TFTPIMAGE := /tftpboot/zImage.$(END) +EXTRA := misc-44x.o +endif +ifeq ($(CONFIG_OCOTEA),y) +ZIMAGE := zImage-TREE +ZIMAGEINITRD := zImage.initrd-TREE +END := ocotea +ENTRYPOINT := 0x00800000 +TFTPIMAGE := /tftpboot/zImage.$(END) +EXTRA := misc-44x.o +endif ifeq ($(CONFIG_GEMINI),y) ZIMAGE := zImage-SMON ZIMAGEINITRD := zImage.initrd-SMON -EXTRA := direct.o TFTPIMAGE := /tftpboot/zImage.gemini endif ifeq ($(CONFIG_PAL4),y) ZIMAGE := zImage-PAL4 ZIMAGEINITRD := zImage.initrd-PAL4 -EXTRA := direct.o TFTPIMAGE := /tftpboot/zImage.pal4 endif ifeq ($(CONFIG_SPRUCE),y) ZIMAGE := zImage-TREE ZIMAGEINITRD := zImage.initrd-TREE -EXTRA := direct.o ENTRYPOINT := 0x00800000 MISC := misc-spruce.o END := spruce @@ -60,7 +73,7 @@ ifdef CONFIG_8xx LD_ARGS := -T ../ld.script -Ttext 0x00180000 -Bstatic endif -ifeq ($(CONFIG_8260)$(CONFIG_4xx),y) +ifeq ($(CONFIG_8260)$(CONFIG_40x),y) LD_ARGS := -T ../ld.script -Ttext 0x00400000 -Bstatic endif OBJCOPY_ARGS := -O elf32-powerpc @@ -68,8 +81,9 @@ # head.o and ../common/relocate.o must be at the start. obj-y := head.o ../common/relocate.o $(EXTRA) \ $(MISC) ../common/misc-common.o \ - ../common/string.o ../common/util.o -obj-$(CONFIG_4xx) += embed_config.o + ../common/string.o ../common/util.o \ + ../common/serial_stub.o +obj-$(CONFIG_40x) += embed_config.o obj-$(CONFIG_8xx) += embed_config.o obj-$(CONFIG_8260) += embed_config.o obj-$(CONFIG_BSEIP) += iic.o diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/boot/simple/direct.S cset-v2.4.20/arch/ppc/boot/simple/direct.S --- cset-v2.4.20~/arch/ppc/boot/simple/direct.S 2004-10-25 15:00:34.000000000 +0900 +++ cset-v2.4.20/arch/ppc/boot/simple/direct.S 1970-01-01 09:00:00.000000000 +0900 @@ -1,15 +0,0 @@ -/* - * arch/ppc/boot/simple/direct.S - * - * Author: Tom Rini - * - * This is an empty function for machines which use SERIAL_IO_MEM - * and don't need ISA_io set to anything but 0, or perform any other - * serial fixups. - */ - - .text - - .globl serial_fixups -serial_fixups: - blr diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/boot/simple/m8260_tty.c cset-v2.4.20/arch/ppc/boot/simple/m8260_tty.c --- cset-v2.4.20~/arch/ppc/boot/simple/m8260_tty.c 2004-10-25 15:05:41.000000000 +0900 +++ cset-v2.4.20/arch/ppc/boot/simple/m8260_tty.c 2004-11-01 22:35:09.000000000 +0900 @@ -316,8 +316,3 @@ return(!(rbdf->cbd_sc & BD_SC_EMPTY)); } - -void -serial_close(unsigned long com_port) -{ -} diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/boot/simple/m8xx_tty.c cset-v2.4.20/arch/ppc/boot/simple/m8xx_tty.c --- cset-v2.4.20~/arch/ppc/boot/simple/m8xx_tty.c 2004-10-25 15:03:06.000000000 +0900 +++ cset-v2.4.20/arch/ppc/boot/simple/m8xx_tty.c 2004-11-01 22:35:09.000000000 +0900 @@ -293,8 +293,3 @@ return(!(rbdf->cbd_sc & BD_SC_EMPTY)); } - -void -serial_close(unsigned long com_port) -{ -} diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/boot/simple/misc-44x.c cset-v2.4.20/arch/ppc/boot/simple/misc-44x.c --- cset-v2.4.20~/arch/ppc/boot/simple/misc-44x.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/boot/simple/misc-44x.c 2004-11-01 22:35:09.000000000 +0900 @@ -0,0 +1,32 @@ +/* + * arch/ppc/simple/misc-44x.c + * + * Misc. bootloader code for IBM PPC 44x reference boards (Ebony, Ocotea) + * + * Matt Porter + * Eugene Surovegin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include + +extern struct bi_record *decompress_kernel(unsigned long load_addr, + int num_words, unsigned long cksum); + +struct bi_record * +load_kernel(unsigned long load_addr, int num_words, unsigned long cksum) +{ + mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR); /* reset MAL */ + while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; /* wait for reset */ + *(volatile unsigned long *)PPC44x_EMAC0_MR0 = 0x20000000; /* reset EMAC */ + eieio(); + + return decompress_kernel(load_addr, num_words, cksum); +} diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/boot/simple/misc-embedded.c cset-v2.4.20/arch/ppc/boot/simple/misc-embedded.c --- cset-v2.4.20~/arch/ppc/boot/simple/misc-embedded.c 2004-10-25 15:03:37.000000000 +0900 +++ cset-v2.4.20/arch/ppc/boot/simple/misc-embedded.c 2004-11-01 22:35:09.000000000 +0900 @@ -28,6 +28,10 @@ #include "nonstdio.h" #include "zlib.h" +#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_VGA_CONSOLE) +#define INTERACTIVE_CONSOLE 1 +#endif + /* The linker tells us where the image is. */ extern char __image_begin, __image_end; extern char __ramdisk_begin, __ramdisk_end; @@ -79,17 +83,19 @@ unsigned long decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum, bd_t *bp) { - char *cp, ch; - int timer = 0, zimage_size; +#ifdef INTERACTIVE_CONSOLE + int timer = 0; + char ch; +#endif + char *cp; + int zimage_size; unsigned long initrd_size; /* First, capture the embedded board information. Then * initialize the serial console port. */ embed_config(&bp); -#ifdef CONFIG_SERIAL_CONSOLE com_port = serial_init(0, bp); -#endif /* copy board data */ if (bp) @@ -172,7 +178,7 @@ #endif while ( *cp ) putc(*cp++); -#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_VGA_CONSOLE) +#ifdef INTERACTIVE_CONSOLE /* * If they have a console, allow them to edit the command line. * Otherwise, don't bother wasting the five seconds. diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/boot/simple/misc-spruce.c cset-v2.4.20/arch/ppc/boot/simple/misc-spruce.c --- cset-v2.4.20~/arch/ppc/boot/simple/misc-spruce.c 2004-10-25 15:03:43.000000000 +0900 +++ cset-v2.4.20/arch/ppc/boot/simple/misc-spruce.c 2004-11-01 22:35:09.000000000 +0900 @@ -43,6 +43,16 @@ #include "zlib.h" +#ifdef CONFIG_CMDLINE +#define CMDLINE CONFIG_CMDLINE +#else +#define CMDLINE "" +#endif + +#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_VGA_CONSOLE) +#define INTERACTIVE_CONSOLE 1 +#endif + /* Define some important locations of the Spruce. */ #define SPRUCE_PCI_CONFIG_ADDR 0xfec00000 #define SPRUCE_PCI_CONFIG_DATA 0xfec00004 @@ -58,11 +68,6 @@ extern char __ramdisk_begin, __ramdisk_end; extern char _end[]; -#ifdef CONFIG_CMDLINE -#define CMDLINE CONFIG_CMDLINE -#else -#define CMDLINE "" -#endif char cmd_preset[] = CMDLINE; char cmd_buf[256]; char *cmd_line = cmd_buf; @@ -166,9 +171,11 @@ unsigned long decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum) { +#ifdef INTERACTIVE_CONSOLE int timer = 0; - char *cp, ch; - + char ch; +#endif + char *cp; int loop; int csr0; int csr_id; @@ -189,10 +196,8 @@ unsigned char header_type; unsigned int bar0; -#ifdef CONFIG_SERIAL_CONSOLE /* Initialize the serial console port */ com_port = serial_init(0, NULL); -#endif /* * Gah, these firmware guys need to learn that hardware @@ -367,7 +372,13 @@ puts("\nLinux/PPC load: "); cp = cmd_line; memcpy (cmd_line, cmd_preset, sizeof(cmd_preset)); - while ( *cp ) putc(*cp++); + while ( *cp ) + putc(*cp++); +#ifdef INTERACTIVE_CONSOLE + /* + * If they have a console, allow them to edit the command line. + * Otherwise, don't bother wasting the five seconds. + */ while (timer++ < 5*1000) { if (tstc()) { while ((ch = getc()) != '\n' && ch != '\r') { @@ -385,6 +396,7 @@ } udelay(1000); /* 1 msec */ } +#endif *cp = 0; puts("\n"); バイナリー・ファイルcset-v2.4.20~/arch/ppc/boot/utils/mktreeとcset-v2.4.20/arch/ppc/boot/utils/mktreeは違います diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/config.in cset-v2.4.20/arch/ppc/config.in --- cset-v2.4.20~/arch/ppc/config.in 2004-10-25 14:58:34.000000000 +0900 +++ cset-v2.4.20/arch/ppc/config.in 2004-11-01 22:35:09.000000000 +0900 @@ -30,11 +30,16 @@ define_bool CONFIG_PPC32 y choice 'Processor Type' \ "6xx/7xx/74xx/8260 CONFIG_6xx \ - 4xx CONFIG_4xx \ + 40x CONFIG_40x \ + 44x CONFIG_44x \ POWER3 CONFIG_POWER3 \ POWER4 CONFIG_POWER4 \ 8xx CONFIG_8xx" 6xx +if [ "$CONFIG_40x" = "y" -o "$CONFIG_44x" = "y" ]; then + define_bool CONFIG_4xx y +fi + if [ "$CONFIG_6xx" = "y" ]; then bool 'MPC8260 CPM Support' CONFIG_8260 fi @@ -57,11 +62,16 @@ bool 'Support for EST8260' CONFIG_EST8260 fi -if [ "$CONFIG_4xx" = "y" ]; then +if [ "$CONFIG_40x" = "y" ]; then choice 'Machine Type' \ "Oak CONFIG_OAK \ Walnut CONFIG_WALNUT" Oak fi +if [ "$CONFIG_44x" = "y" ]; then + choice 'Machine Type' \ + "Ebony CONFIG_EBONY \ + Ocotea CONFIG_OCOTEA" Ebony +fi if [ "$CONFIG_8xx" = "y" ]; then define_bool CONFIG_SERIAL_CONSOLE y @@ -126,6 +136,95 @@ bool 'Math emulation' CONFIG_MATH_EMULATION fi +if [ "$CONFIG_4xx" = "y" ]; then + + bool 'PPC4xx DMA controller support' CONFIG_PPC4xx_DMA + if [ "$CONFIG_PPC4xx_DMA" = "y" ]; then + define_bool CONFIG_PPC4xx_EDMA y + fi + +# +# Set generic PPC4xx options +# + define_bool CONFIG_NOT_COHERENT_CACHE y + + if [ "$CONFIG_40x" = "y" ]; then + choice 'TTYS0 device and default console' \ + "UART0 CONFIG_UART0_TTYS0 \ + UART1 CONFIG_UART0_TTYS1" UART0 + fi + +# +# Set processor implementation based on board +# + if [ "$CONFIG_OAK" = "y" -o "$CONFIG_TIVO" = "y" ]; then + define_bool CONFIG_403GCX y + fi + + if [ "$CONFIG_WALNUT" = "y" ]; then + define_bool CONFIG_405GP y + fi + + if [ "$CONFIG_EBONY" = "y" ]; then + define_bool CONFIG_440GP y + fi + + if [ "$CONFIG_OCOTEA" = "y" ]; then + define_bool CONFIG_440GX y + fi + +# +# Set options based on processor implementation +# + if [ "$CONFIG_405GP" = "y" ]; then + define_bool CONFIG_IBM_OCP y + define_bool CONFIG_405 y + fi + + if [ "$CONFIG_440GP" = "y" ]; then + define_bool CONFIG_IBM_OCP y + define_bool CONFIG_GEN550 y + define_bool CONFIG_440 y + fi + + if [ "$CONFIG_440GX" = "y" ]; then + define_bool CONFIG_IBM_OCP y + define_bool CONFIG_GEN550 y + define_bool CONFIG_IBM_EMAC4 y + define_bool CONFIG_440A y + fi + +# +# Set options based on processor core +# + if [ "$CONFIG_40x" = "y" ]; then + define_bool CONFIG_IBM405_ERR51 y + fi + + if [ "$CONFIG_405" = "y" ]; then + define_bool CONFIG_IBM405_ERR77 y + fi + + if [ "$CONFIG_44x" = "y" ]; then + define_bool CONFIG_PTE_64BIT y + define_bool CONFIG_PIN_TLB y + define_bool CONFIG_BOOKE y + fi + +# +# Set other board specific options +# + if [ "$CONFIG_OAK" = "y" -o "$CONFIG_TIVO" = "y" -o \ + "$CONFIG_WALNUT" = "y" ]; then + define_bool CONFIG_IBM_OPENBIOS y + fi + + if [ "$CONFIG_WALNUT" = "y" ]; then + define_bool CONFIG_BIOS_FIXUP y + fi + +fi + if [ "$CONFIG_8xx" = "y" -o "$CONFIG_8260" = "y" ]; then define_bool CONFIG_EMBEDDEDBOOT y fi @@ -144,7 +243,8 @@ define_bool CONFIG_MCA n if [ "$CONFIG_4xx" = "y" -o "$CONFIG_8260" = "y" ]; then - define_bool CONFIG_PCI n + bool "Enable PCI" CONFIG_PCI + bool 'PC PS/2 style Keyboard' CONFIG_PC_KEYBOARD else if [ "$CONFIG_8xx" = "y" ]; then bool 'QSpan PCI' CONFIG_PCI_QSPAN @@ -316,7 +416,7 @@ mainmenu_option next_comment comment 'Console drivers' -if [ "$CONFIG_4xx" != "y" -a "$CONFIG_8xx" != "y" ]; then +if [ "$CONFIG_40x" != "y" -a "$CONFIG_8xx" != "y" ]; then bool 'Support for VGA Console' CONFIG_VGA_CONSOLE fi source drivers/video/Config.in diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/configs/ebony_defconfig cset-v2.4.20/arch/ppc/configs/ebony_defconfig --- cset-v2.4.20~/arch/ppc/configs/ebony_defconfig 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/configs/ebony_defconfig 2004-11-01 22:35:09.000000000 +0900 @@ -0,0 +1,491 @@ +# +# Automatically generated by make menuconfig: don't edit +# +# CONFIG_UID16 is not set +# CONFIG_RWSEM_GENERIC_SPINLOCK is not set +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_HAVE_DEC_LOCK=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODVERSIONS is not set +CONFIG_KMOD=y + +# +# Platform support +# +CONFIG_PPC=y +CONFIG_PPC32=y +# CONFIG_6xx is not set +# CONFIG_40x is not set +CONFIG_44x=y +# CONFIG_POWER3 is not set +# CONFIG_POWER4 is not set +# CONFIG_8xx is not set +CONFIG_4xx=y +CONFIG_EBONY=y +# CONFIG_OCOTEA is not set +# CONFIG_SMP is not set +# CONFIG_MATH_EMULATION is not set +# CONFIG_PPC4xx_DMA is not set +CONFIG_NOT_COHERENT_CACHE=y +CONFIG_440GP=y +CONFIG_IBM_OCP=y +CONFIG_GEN550=y +CONFIG_440=y +CONFIG_PTE_64BIT=y +CONFIG_PIN_TLB=y +CONFIG_BOOKE=y + +# +# General setup +# +CONFIG_HIGHMEM=y +# CONFIG_ISA is not set +# CONFIG_EISA is not set +# CONFIG_SBUS is not set +# CONFIG_MCA is not set +CONFIG_PCI=y +# CONFIG_PC_KEYBOARD is not set +CONFIG_NET=y +CONFIG_SYSCTL=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +CONFIG_KERNEL_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_PCI_NAMES=y +# CONFIG_HOTPLUG is not set +# CONFIG_PCMCIA is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set +CONFIG_GEN_RTC=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="ip=on" + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Plug and Play configuration +# +# CONFIG_PNP is not set +# CONFIG_ISAPNP is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_CISS_SCSI_TAPE is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_STATS=y + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set +# CONFIG_BLK_DEV_MD is not set +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +# CONFIG_MD_RAID1 is not set +# CONFIG_MD_RAID5 is not set +# CONFIG_MD_MULTIPATH is not set +# CONFIG_BLK_DEV_LVM is not set + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +# CONFIG_NETLINK_DEV is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_FILTER=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_COMPAT_IPCHAINS is not set +# CONFIG_IP_NF_COMPAT_IPFWADM is not set +# CONFIG_IPV6 is not set +# CONFIG_KHTTPD is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set + +# +# Appletalk devices +# +# CONFIG_DEV_APPLETALK is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_LLC is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set + +# +# ATA/IDE/MFM/RLL support +# +# CONFIG_IDE is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# IEEE 1394 (FireWire) support (EXPERIMENTAL) +# +# CONFIG_IEEE1394 is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +# CONFIG_NET_ETHERNET is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_MYRI_SBUS is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# On-chip net devices +# +CONFIG_IBM_OCP_ENET=y +# CONFIG_IBM_OCP_ENET_ERROR_MSG is not set +CONFIG_IBM_OCP_ENET_RX_BUFF=64 +CONFIG_IBM_OCP_ENET_TX_BUFF=8 +CONFIG_IBM_OCP_ENET_GAP=8 +CONFIG_IBM_OCP_ENET_SKB_RES=0 +CONFIG_OCP_NET=y +CONFIG_IBM_OCP_MAL_CNT=1 +CONFIG_IBM_OCP_ZMII=y +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PLIP is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set +# CONFIG_NET_FC is not set +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Old CD-ROM drivers (not SCSI, not IDE) +# +# CONFIG_CD_NO_IDESCSI is not set + +# +# Console drivers +# +# CONFIG_VGA_CONSOLE is not set + +# +# Frame-buffer support +# +# CONFIG_FB is not set + +# +# Input core support +# +# CONFIG_INPUT is not set +# CONFIG_INPUT_KEYBDEV is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set + +# +# Macintosh device drivers +# + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_SERIAL=y +CONFIG_SERIAL_CONSOLE=y +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set + +# +# Joysticks +# +# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_IPMI_PANIC_EVENT is not set +# CONFIG_IPMI_DEVICE_INTERFACE is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_IPMI_WATCHDOG is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_SCx200_GPIO is not set +# CONFIG_AMD_PM768 is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_IBM_GPIO is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_QFMT_V2 is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BEFS_DEBUG is not set +# CONFIG_BFS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_JBD_DEBUG is not set +# CONFIG_FAT_FS is not set +# CONFIG_MSDOS_FS is not set +# CONFIG_UMSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y +# CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_JFS_FS is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set +CONFIG_DEVPTS_FS=y +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_EXT2_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set +# CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_DIRECTIO is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_SUNRPC=y +CONFIG_LOCKD=y +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_ZISOFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_SMB_NLS is not set +# CONFIG_NLS is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB is not set + +# +# Bluetooth support +# +# CONFIG_BLUEZ is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_CRC32=y +# CONFIG_ZLIB_INFLATE is not set +# CONFIG_ZLIB_DEFLATE is not set + +# +# Kernel hacking +# +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SERIAL_TEXT_DEBUG is not set diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/configs/ocotea_defconfig cset-v2.4.20/arch/ppc/configs/ocotea_defconfig --- cset-v2.4.20~/arch/ppc/configs/ocotea_defconfig 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/configs/ocotea_defconfig 2004-11-02 18:03:46.000000000 +0900 @@ -0,0 +1,455 @@ +# +# Automatically generated make config: don't edit +# +# CONFIG_UID16 is not set +# CONFIG_RWSEM_GENERIC_SPINLOCK is not set +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_HAVE_DEC_LOCK=y + +# +# Code maturity level options +# +# CONFIG_EXPERIMENTAL is not set + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# Platform support +# +CONFIG_PPC=y +CONFIG_PPC32=y +# CONFIG_6xx is not set +# CONFIG_40x is not set +CONFIG_44x=y +# CONFIG_POWER3 is not set +# CONFIG_POWER4 is not set +# CONFIG_8xx is not set +CONFIG_4xx=y +# CONFIG_PPC_STD_MMU is not set +# CONFIG_EBONY is not set +CONFIG_OCOTEA=y +# CONFIG_ALL_PPC is not set +# CONFIG_SMP is not set +# CONFIG_MATH_EMULATION is not set +# CONFIG_PPC4xx_DMA is not set +CONFIG_NOT_COHERENT_CACHE=y +CONFIG_440GX=y +CONFIG_IBM_OCP=y +CONFIG_GEN550=y +CONFIG_IBM_EMAC4=y +CONFIG_440A=y +CONFIG_PTE_64BIT=y +CONFIG_PIN_TLB=y +CONFIG_BOOKE=y + +# +# General setup +# +# CONFIG_HIGHMEM is not set +# CONFIG_ISA is not set +# CONFIG_EISA is not set +# CONFIG_SBUS is not set +# CONFIG_MCA is not set +CONFIG_PCI=y +# CONFIG_PC_KEYBOARD is not set +CONFIG_NET=y +# CONFIG_SYSCTL is not set +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +CONFIG_KERNEL_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_PCI_NAMES is not set +# CONFIG_HOTPLUG is not set +# CONFIG_PCMCIA is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="ip=on console=ttyS0,115200" + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Plug and Play configuration +# +# CONFIG_PNP is not set +# CONFIG_ISAPNP is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_CISS_SCSI_TAPE is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_BLK_STATS is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set +# CONFIG_BLK_DEV_MD is not set +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +# CONFIG_MD_RAID1 is not set +# CONFIG_MD_RAID5 is not set +# CONFIG_MD_MULTIPATH is not set +# CONFIG_BLK_DEV_LVM is not set + +# +# Networking options +# +# CONFIG_PACKET is not set +# CONFIG_NETLINK_DEV is not set +# CONFIG_NETFILTER is not set +# CONFIG_FILTER is not set +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_VLAN_8021Q is not set + +# +# +# +# CONFIG_IPX is not set +# CONFIG_ATALK is not set + +# +# Appletalk devices +# +# CONFIG_DEV_APPLETALK is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set + +# +# ATA/IDE/MFM/RLL support +# +# CONFIG_IDE is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# Ethernet (10 or 100Mbit) +# +# CONFIG_NET_ETHERNET is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +# CONFIG_MYRI_SBUS is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# On-chip net devices +# +CONFIG_IBM_OCP_ENET=y +# CONFIG_IBM_OCP_ENET_ERROR_MSG is not set +CONFIG_IBM_OCP_ENET_RX_BUFF=64 +CONFIG_IBM_OCP_ENET_TX_BUFF=8 +CONFIG_IBM_OCP_ENET_GAP=8 +CONFIG_IBM_OCP_ENET_SKB_RES=0 +CONFIG_OCP_NET=y +# CONFIG_FDDI is not set +# CONFIG_PLIP is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set +# CONFIG_NET_FC is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Old CD-ROM drivers (not SCSI, not IDE) +# +# CONFIG_CD_NO_IDESCSI is not set + +# +# Console drivers +# +# CONFIG_VGA_CONSOLE is not set + +# +# Frame-buffer support +# +# CONFIG_FB is not set + +# +# Input core support +# +# CONFIG_INPUT is not set +# CONFIG_INPUT_KEYBDEV is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set + +# +# Macintosh device drivers +# + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_SERIAL=y +CONFIG_SERIAL_CONSOLE=y +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +CONFIG_I2C=y +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_PROC=y + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set + +# +# Joysticks +# +# CONFIG_INPUT_GAMEPORT is not set + +# +# Input core support is needed for gameports +# + +# +# Input core support is needed for joysticks +# +# CONFIG_QIC02_TAPE is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_AMD_PM768 is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BEFS_DEBUG is not set +# CONFIG_BFS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_JBD_DEBUG is not set +# CONFIG_FAT_FS is not set +# CONFIG_MSDOS_FS is not set +# CONFIG_UMSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +CONFIG_TMPFS=y +CONFIG_RAMFS=y +# CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_JFS_FS is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set +CONFIG_DEVPTS_FS=y +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_EXT2_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set +# CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_SUNRPC=y +CONFIG_LOCKD=y +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_ZISOFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_SMB_NLS is not set +# CONFIG_NLS is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB is not set + +# +# Bluetooth support +# +# CONFIG_BLUEZ is not set + +# +# Library routines +# +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y + +# +# Kernel hacking +# +# CONFIG_DEBUG_KERNEL is not set diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/configs/walnut_defconfig cset-v2.4.20/arch/ppc/configs/walnut_defconfig --- cset-v2.4.20~/arch/ppc/configs/walnut_defconfig 2004-10-25 15:02:07.000000000 +0900 +++ cset-v2.4.20/arch/ppc/configs/walnut_defconfig 2004-11-01 22:35:09.000000000 +0900 @@ -291,7 +291,8 @@ CONFIG_SERIAL_CONSOLE=y # CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_UNIX98_PTYS is not set +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 # # I2C support @@ -388,7 +389,7 @@ # CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_MOUNT is not set # CONFIG_DEVFS_DEBUG is not set -# CONFIG_DEVPTS_FS is not set +CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set # CONFIG_QNX4FS_RW is not set # CONFIG_ROMFS_FS is not set @@ -427,8 +428,18 @@ # # Partition Types # -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +# CONFIG_MSDOS_PARTITION is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_EFI_PARTITION is not set # CONFIG_SMB_NLS is not set # CONFIG_NLS is not set @@ -450,10 +461,11 @@ # # Library routines # -# CONFIG_ZLIB_INFLATE is not set -# CONFIG_ZLIB_DEFLATE is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y # # Kernel hacking # # CONFIG_DEBUG_KERNEL is not set +# CONFIG_SERIAL_TEXT_DEBUG is not set diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/defconfig cset-v2.4.20/arch/ppc/defconfig --- cset-v2.4.20~/arch/ppc/defconfig 2004-10-25 15:01:50.000000000 +0900 +++ cset-v2.4.20/arch/ppc/defconfig 2004-11-02 18:03:37.000000000 +0900 @@ -9,38 +9,41 @@ # # Code maturity level options # -CONFIG_EXPERIMENTAL=y +# CONFIG_EXPERIMENTAL is not set # # Loadable module support # -CONFIG_MODULES=y -CONFIG_MODVERSIONS=y -CONFIG_KMOD=y +# CONFIG_MODULES is not set # # Platform support # CONFIG_PPC=y CONFIG_PPC32=y -CONFIG_6xx=y -# CONFIG_4xx is not set +# CONFIG_6xx is not set +# CONFIG_40x is not set +CONFIG_44x=y # CONFIG_POWER3 is not set # CONFIG_POWER4 is not set # CONFIG_8xx is not set -# CONFIG_8260 is not set -CONFIG_PPC_STD_MMU=y -CONFIG_ALL_PPC=y -# CONFIG_APUS is not set -# CONFIG_SPRUCE is not set -# CONFIG_PAL4 is not set -# CONFIG_GEMINI is not set +CONFIG_4xx=y +# CONFIG_PPC_STD_MMU is not set +# CONFIG_EBONY is not set +CONFIG_OCOTEA=y +# CONFIG_ALL_PPC is not set # CONFIG_SMP is not set -CONFIG_ALTIVEC=y -CONFIG_TAU=y -# CONFIG_TAU_INT is not set -# CONFIG_TAU_AVERAGE is not set -CONFIG_PPC_ISATIMER=y +# CONFIG_MATH_EMULATION is not set +# CONFIG_PPC4xx_DMA is not set +CONFIG_NOT_COHERENT_CACHE=y +CONFIG_440GX=y +CONFIG_IBM_OCP=y +CONFIG_GEN550=y +CONFIG_IBM_EMAC4=y +CONFIG_440A=y +CONFIG_PTE_64BIT=y +CONFIG_PIN_TLB=y +CONFIG_BOOKE=y # # General setup @@ -51,35 +54,25 @@ # CONFIG_SBUS is not set # CONFIG_MCA is not set CONFIG_PCI=y +# CONFIG_PC_KEYBOARD is not set CONFIG_NET=y -CONFIG_SYSCTL=y -CONFIG_SYSVIPC=y +# CONFIG_SYSCTL is not set +# CONFIG_SYSVIPC is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_KCORE_ELF=y CONFIG_BINFMT_ELF=y CONFIG_KERNEL_ELF=y -CONFIG_BINFMT_MISC=m -CONFIG_PCI_NAMES=y -CONFIG_HOTPLUG=y - -# -# PCMCIA/CardBus support -# +# CONFIG_BINFMT_MISC is not set +# CONFIG_PCI_NAMES is not set +# CONFIG_HOTPLUG is not set # CONFIG_PCMCIA is not set # # Parallel port support # # CONFIG_PARPORT is not set -CONFIG_PPC_RTC=y -CONFIG_PPC601_SYNC_FIX=y -CONFIG_PROC_DEVICETREE=y -CONFIG_PPC_RTAS=y -CONFIG_BOOTX_TEXT=y -CONFIG_PREP_RESIDUAL=y -CONFIG_PROC_PREPRESIDUAL=y CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="console=ttyS0,9600 console=tty0 root=/dev/sda2" +CONFIG_CMDLINE="ip=on console=ttyS0,115200" # # Memory Technology Devices (MTD) @@ -95,7 +88,7 @@ # # Block devices # -CONFIG_BLK_DEV_FD=m +# CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_XD is not set # CONFIG_PARIDE is not set # CONFIG_BLK_CPQ_DA is not set @@ -103,11 +96,10 @@ # CONFIG_CISS_SCSI_TAPE is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set -CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_INITRD=y +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set # CONFIG_BLK_STATS is not set # @@ -125,79 +117,30 @@ # # Networking options # -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set +# CONFIG_PACKET is not set # CONFIG_NETLINK_DEV is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_NETFILTER is not set # CONFIG_FILTER is not set CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set # CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set # CONFIG_INET_ECN is not set -CONFIG_SYN_COOKIES=y - -# -# IP: Netfilter Configuration -# -CONFIG_IP_NF_CONNTRACK=m -CONFIG_IP_NF_FTP=m -CONFIG_IP_NF_IRC=m -# CONFIG_IP_NF_QUEUE is not set -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_LIMIT=m -CONFIG_IP_NF_MATCH_MAC=m -CONFIG_IP_NF_MATCH_PKTTYPE=m -CONFIG_IP_NF_MATCH_MARK=m -CONFIG_IP_NF_MATCH_MULTIPORT=m -CONFIG_IP_NF_MATCH_TOS=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_DSCP=m -CONFIG_IP_NF_MATCH_AH_ESP=m -CONFIG_IP_NF_MATCH_LENGTH=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_TCPMSS=m -CONFIG_IP_NF_MATCH_HELPER=m -CONFIG_IP_NF_MATCH_STATE=m -CONFIG_IP_NF_MATCH_CONNTRACK=m -CONFIG_IP_NF_MATCH_UNCLEAN=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_MIRROR=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -# CONFIG_IP_NF_NAT_LOCAL is not set -CONFIG_IP_NF_NAT_SNMP_BASIC=m -CONFIG_IP_NF_NAT_IRC=m -CONFIG_IP_NF_NAT_FTP=m -# CONFIG_IP_NF_MANGLE is not set -# CONFIG_IP_NF_TARGET_LOG is not set -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_IP_NF_TARGET_TCPMSS=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_COMPAT_IPCHAINS=m -CONFIG_IP_NF_NAT_NEEDED=y -# CONFIG_IP_NF_COMPAT_IPFWADM is not set -# CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set +# CONFIG_SYN_COOKIES is not set # CONFIG_VLAN_8021Q is not set # # # # CONFIG_IPX is not set -CONFIG_ATALK=m +# CONFIG_ATALK is not set # # Appletalk devices @@ -205,14 +148,6 @@ # CONFIG_DEV_APPLETALK is not set # CONFIG_DECNET is not set # CONFIG_BRIDGE is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_LLC is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_FASTROUTE is not set -# CONFIG_NET_HW_FLOWCONTROL is not set # # QoS and/or fair queueing @@ -227,185 +162,14 @@ # # ATA/IDE/MFM/RLL support # -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set +# CONFIG_IDE is not set +# CONFIG_BLK_DEV_IDE_MODES is not set # CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_IDEDISK_STROKE is not set -# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set -# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set -# CONFIG_BLK_DEV_IDEDISK_IBM is not set -# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set -# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set -# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set -# CONFIG_BLK_DEV_IDEDISK_WD is not set -# CONFIG_BLK_DEV_COMMERIAL is not set -# CONFIG_BLK_DEV_TIVO is not set -# CONFIG_BLK_DEV_IDECS is not set -CONFIG_BLK_DEV_IDECD=y -# CONFIG_BLK_DEV_IDETAPE is not set -CONFIG_BLK_DEV_IDEFLOPPY=y -CONFIG_BLK_DEV_IDESCSI=y -# CONFIG_IDE_TASK_IOCTL is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -CONFIG_BLK_DEV_IDEPCI=y -CONFIG_IDEPCI_SHARE_IRQ=y -CONFIG_BLK_DEV_IDEDMA_PCI=y -# CONFIG_BLK_DEV_OFFBOARD is not set -# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -CONFIG_IDEDMA_PCI_AUTO=y -# CONFIG_IDEDMA_ONLYDISK is not set -CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_PCI_WIP is not set -# CONFIG_BLK_DEV_IDEDMA_TIMEOUT is not set -# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set -CONFIG_BLK_DEV_ADMA=y -# CONFIG_BLK_DEV_AEC62XX is not set -# CONFIG_AEC62XX_TUNING is not set -# CONFIG_BLK_DEV_ALI15X3 is not set -# CONFIG_WDC_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD74XX is not set -# CONFIG_AMD74XX_OVERRIDE is not set -CONFIG_BLK_DEV_CMD64X=y -# CONFIG_BLK_DEV_CMD680 is not set -# CONFIG_BLK_DEV_CY82C693 is not set -# CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set -# CONFIG_HPT34X_AUTODMA is not set -# CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_BLK_DEV_NS87415 is not set -# CONFIG_BLK_DEV_OPTI621 is not set -# CONFIG_BLK_DEV_PDC202XX is not set -# CONFIG_PDC202XX_BURST is not set -# CONFIG_PDC202XX_FORCE is not set -# CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_SIS5513 is not set -# CONFIG_BLK_DEV_SLC90E66 is not set -# CONFIG_BLK_DEV_TRM290 is not set -# CONFIG_BLK_DEV_VIA82CXXX is not set -CONFIG_BLK_DEV_SL82C105=y -CONFIG_BLK_DEV_IDE_PMAC=y -CONFIG_BLK_DEV_IDEDMA_PMAC=y -CONFIG_BLK_DEV_IDEDMA_PMAC_AUTO=y -CONFIG_BLK_DEV_IDEDMA=y -CONFIG_BLK_DEV_IDEPCI=y -# CONFIG_IDE_CHIPSETS is not set -CONFIG_IDEDMA_AUTO=y -# CONFIG_IDEDMA_IVB is not set -# CONFIG_DMA_NONPCI is not set -CONFIG_BLK_DEV_IDE_MODES=y -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set # # SCSI support # -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -CONFIG_CHR_DEV_ST=y -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_SR_EXTRA_DEVS=2 -CONFIG_CHR_DEV_SG=y - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AACRAID is not set -CONFIG_SCSI_AIC7XXX=m -CONFIG_AIC7XXX_CMDS_PER_DEVICE=253 -CONFIG_AIC7XXX_RESET_DELAY_MS=15000 -# CONFIG_AIC7XXX_PROBE_EISA_VL is not set -# CONFIG_AIC7XXX_BUILD_FIRMWARE is not set -CONFIG_SCSI_AIC7XXX_OLD=m -# CONFIG_AIC7XXX_OLD_TCQ_ON_BY_DEFAULT is not set -CONFIG_AIC7XXX_OLD_CMDS_PER_DEVICE=8 -CONFIG_AIC7XXX_OLD_PROC_STATS=y -# CONFIG_SCSI_DPT_I2O is not set -CONFIG_SCSI_ADVANSYS=m -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR53C7xx is not set -CONFIG_SCSI_SYM53C8XX_2=y -CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0 -CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 -CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 -# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -# CONFIG_SCSI_QLOGIC_FC is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set -CONFIG_SCSI_MESH=y -CONFIG_SCSI_MESH_SYNC_RATE=5 -CONFIG_SCSI_MESH_RESET_DELAY_MS=4000 -CONFIG_SCSI_MAC53C94=y - -# -# IEEE 1394 (FireWire) support (EXPERIMENTAL) -# -# CONFIG_IEEE1394 is not set +# CONFIG_SCSI is not set # # Network device support @@ -420,112 +184,50 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) # -CONFIG_NET_ETHERNET=y -CONFIG_MACE=y -# CONFIG_MACE_AAUI_PORT is not set -CONFIG_BMAC=y -CONFIG_GMAC=y -# CONFIG_SUNLANCE is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -CONFIG_NET_PCI=y -CONFIG_PCNET32=y -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_APRICOT is not set -# CONFIG_CS89x0 is not set -CONFIG_TULIP=y -# CONFIG_TULIP_MWI is not set -CONFIG_TULIP_MMIO=y -CONFIG_DE4X5=m -# CONFIG_DGRS is not set -# CONFIG_DM9102 is not set -# CONFIG_EEPRO100 is not set -# CONFIG_E100 is not set -# CONFIG_LNE390 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_NE3210 is not set -# CONFIG_ES3210 is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_8139TOO_PIO is not set -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139TOO_8129 is not set -# CONFIG_8139_OLD_RX_RESET is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_SUNDANCE_MMIO is not set -# CONFIG_TLAN is not set -# CONFIG_TC35815 is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_VIA_RHINE_MMIO is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_NET_POCKET is not set +# CONFIG_NET_ETHERNET is not set # # Ethernet (1000 Mbit) # # CONFIG_ACENIC is not set # CONFIG_DL2K is not set -# CONFIG_E1000 is not set +CONFIG_E1000=y # CONFIG_MYRI_SBUS is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set + +# +# On-chip net devices +# +CONFIG_IBM_OCP_ENET=y +# CONFIG_IBM_OCP_ENET_ERROR_MSG is not set +CONFIG_IBM_OCP_ENET_RX_BUFF=64 +CONFIG_IBM_OCP_ENET_TX_BUFF=8 +CONFIG_IBM_OCP_ENET_GAP=8 +CONFIG_IBM_OCP_ENET_SKB_RES=0 +CONFIG_OCP_NET=y # CONFIG_FDDI is not set -# CONFIG_HIPPI is not set # CONFIG_PLIP is not set -CONFIG_PPP=y -CONFIG_PPP_MULTILINK=y -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=y -# CONFIG_PPP_SYNC_TTY is not set -CONFIG_PPP_DEFLATE=y -# CONFIG_PPP_BSDCOMP is not set -# CONFIG_PPPOE is not set +# CONFIG_PPP is not set # CONFIG_SLIP is not set # # Wireless LAN (non-hamradio) # -CONFIG_NET_RADIO=y -# CONFIG_STRIP is not set -# CONFIG_WAVELAN is not set -# CONFIG_ARLAN is not set -# CONFIG_AIRONET4500 is not set -# CONFIG_AIRONET4500_NONCS is not set -# CONFIG_AIRONET4500_PROC is not set -# CONFIG_AIRO is not set -CONFIG_HERMES=m -CONFIG_APPLE_AIRPORT=m -# CONFIG_PLX_HERMES is not set -# CONFIG_PCI_HERMES is not set -CONFIG_NET_WIRELESS=y +# CONFIG_NET_RADIO is not set # # Token Ring devices # # CONFIG_TR is not set # CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set # # Wan interfaces @@ -555,164 +257,72 @@ # # Console drivers # -CONFIG_VGA_CONSOLE=y +# CONFIG_VGA_CONSOLE is not set # # Frame-buffer support # -CONFIG_FB=y -CONFIG_DUMMY_CONSOLE=y -# CONFIG_FB_RIVA is not set -# CONFIG_FB_CLGEN is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_PM3 is not set -# CONFIG_FB_CYBER2000 is not set -CONFIG_FB_OF=y -CONFIG_FB_CONTROL=y -CONFIG_FB_PLATINUM=y -CONFIG_FB_VALKYRIE=y -CONFIG_FB_CT65550=y -CONFIG_FB_IMSTT=y -# CONFIG_FB_S3TRIO is not set -# CONFIG_FB_VGA16 is not set -CONFIG_FB_MATROX=y -CONFIG_FB_MATROX_MILLENIUM=y -CONFIG_FB_MATROX_MYSTIQUE=y -# CONFIG_FB_MATROX_G100 is not set -# CONFIG_FB_MATROX_I2C is not set -# CONFIG_FB_MATROX_G450 is not set -# CONFIG_FB_MATROX_MULTIHEAD is not set -CONFIG_FB_ATY=y -CONFIG_FB_ATY_GX=y -CONFIG_FB_ATY_CT=y -CONFIG_FB_RADEON=y -CONFIG_FB_ATY128=y -# CONFIG_FB_SIS is not set -# CONFIG_FB_NEOMAGIC is not set -CONFIG_FB_3DFX=y -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FBCON_ADVANCED is not set -CONFIG_FBCON_CFB8=y -CONFIG_FBCON_CFB16=y -CONFIG_FBCON_CFB24=y -CONFIG_FBCON_CFB32=y -# CONFIG_FBCON_FONTWIDTH8_ONLY is not set -CONFIG_FBCON_FONTS=y -# CONFIG_FONT_8x8 is not set -CONFIG_FONT_8x16=y -CONFIG_FONT_SUN8x16=y -CONFIG_FONT_SUN12x22=y -# CONFIG_FONT_6x11 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FB_COMPAT_XPMAC is not set +# CONFIG_FB is not set # # Input core support # -CONFIG_INPUT=y -CONFIG_INPUT_KEYBDEV=y -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT is not set +# CONFIG_INPUT_KEYBDEV is not set +# CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVDEV is not set # # Macintosh device drivers # -CONFIG_ADB_CUDA=y -CONFIG_ADB_PMU=y -# CONFIG_PMAC_PBOOK is not set -# CONFIG_PMAC_BACKLIGHT is not set -# CONFIG_MAC_FLOPPY is not set -CONFIG_MAC_SERIAL=m -CONFIG_ADB=y -CONFIG_ADB_MACIO=y -CONFIG_INPUT_ADBHID=y -CONFIG_MAC_ADBKEYCODES=y -CONFIG_MAC_EMUMOUSEBTN=y -CONFIG_MAC_HID=y -# CONFIG_ANSLCD is not set # # Character devices # -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_SERIAL=m +# CONFIG_VT is not set +CONFIG_SERIAL=y +CONFIG_SERIAL_CONSOLE=y # CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set # # I2C support # -CONFIG_I2C=m +CONFIG_I2C=y # CONFIG_I2C_ALGOBIT is not set # CONFIG_I2C_ALGOPCF is not set -CONFIG_I2C_KEYWEST=m -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_PROC=m +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_PROC=y # # Mice # -CONFIG_BUSMOUSE=y -# CONFIG_ATIXL_BUSMOUSE is not set -# CONFIG_LOGIBUSMOUSE is not set -# CONFIG_MS_BUSMOUSE is not set -CONFIG_MOUSE=y -CONFIG_PSMOUSE=y -# CONFIG_82C710_MOUSE is not set -# CONFIG_PC110_PAD is not set -# CONFIG_MK712_MOUSE is not set +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set # # Joysticks # # CONFIG_INPUT_GAMEPORT is not set -# CONFIG_INPUT_NS558 is not set -# CONFIG_INPUT_LIGHTNING is not set -# CONFIG_INPUT_PCIGAME is not set -# CONFIG_INPUT_CS461X is not set -# CONFIG_INPUT_EMU10K1 is not set -# CONFIG_INPUT_SERIO is not set -# CONFIG_INPUT_SERPORT is not set # -# Joysticks +# Input core support is needed for gameports +# + +# +# Input core support is needed for joysticks # -# CONFIG_INPUT_ANALOG is not set -# CONFIG_INPUT_A3D is not set -# CONFIG_INPUT_ADI is not set -# CONFIG_INPUT_COBRA is not set -# CONFIG_INPUT_GF2K is not set -# CONFIG_INPUT_GRIP is not set -# CONFIG_INPUT_INTERACT is not set -# CONFIG_INPUT_TMDC is not set -# CONFIG_INPUT_SIDEWINDER is not set -# CONFIG_INPUT_IFORCE_USB is not set -# CONFIG_INPUT_IFORCE_232 is not set -# CONFIG_INPUT_WARRIOR is not set -# CONFIG_INPUT_MAGELLAN is not set -# CONFIG_INPUT_SPACEORB is not set -# CONFIG_INPUT_SPACEBALL is not set -# CONFIG_INPUT_STINGER is not set -# CONFIG_INPUT_DB9 is not set -# CONFIG_INPUT_GAMECON is not set -# CONFIG_INPUT_TURBOGRAFX is not set # CONFIG_QIC02_TAPE is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set -CONFIG_NVRAM=y +# CONFIG_AMD_PM768 is not set +# CONFIG_NVRAM is not set # CONFIG_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set @@ -742,24 +352,24 @@ # CONFIG_ADFS_FS is not set # CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set -CONFIG_HFS_FS=m +# CONFIG_HFS_FS is not set # CONFIG_BEFS_FS is not set # CONFIG_BEFS_DEBUG is not set # CONFIG_BFS_FS is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_JBD_DEBUG is not set -CONFIG_FAT_FS=m -CONFIG_MSDOS_FS=m +# CONFIG_FAT_FS is not set +# CONFIG_MSDOS_FS is not set # CONFIG_UMSDOS_FS is not set -CONFIG_VFAT_FS=m +# CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set # CONFIG_JFFS_FS is not set # CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set CONFIG_TMPFS=y CONFIG_RAMFS=y -CONFIG_ISO9660_FS=y +# CONFIG_ISO9660_FS is not set # CONFIG_JOLIET is not set # CONFIG_ZISOFS is not set # CONFIG_JFS_FS is not set @@ -771,14 +381,14 @@ # CONFIG_NTFS_RW is not set # CONFIG_HPFS_FS is not set CONFIG_PROC_FS=y -CONFIG_DEVFS_FS=y +# CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_MOUNT is not set # CONFIG_DEVFS_DEBUG is not set CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set # CONFIG_QNX4FS_RW is not set # CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UDF_FS is not set # CONFIG_UDF_RW is not set @@ -792,8 +402,8 @@ # CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set -# CONFIG_ROOT_NFS is not set -CONFIG_NFSD=y +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set # CONFIG_NFSD_V3 is not set # CONFIG_NFSD_TCP is not set CONFIG_SUNRPC=y @@ -813,212 +423,20 @@ # # Partition Types # -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -CONFIG_MAC_PARTITION=y +# CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_EFI_PARTITION is not set # CONFIG_SMB_NLS is not set -CONFIG_NLS=y - -# -# Native Language Support -# -CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -CONFIG_NLS_ISO8859_1=m -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set +# CONFIG_NLS is not set # # Sound # -CONFIG_SOUND=m -CONFIG_DMASOUND_PMAC=m -CONFIG_DMASOUND=m -# CONFIG_SOUND_ALI5455 is not set -# CONFIG_SOUND_BT878 is not set -# CONFIG_SOUND_CMPCI is not set -# CONFIG_SOUND_EMU10K1 is not set -# CONFIG_MIDI_EMU10K1 is not set -# CONFIG_SOUND_FUSION is not set -# CONFIG_SOUND_CS4281 is not set -# CONFIG_SOUND_ES1370 is not set -# CONFIG_SOUND_ES1371 is not set -# CONFIG_SOUND_ESSSOLO1 is not set -# CONFIG_SOUND_MAESTRO is not set -# CONFIG_SOUND_MAESTRO3 is not set -# CONFIG_SOUND_FORTE is not set -# CONFIG_SOUND_ICH is not set -# CONFIG_SOUND_RME96XX is not set -# CONFIG_SOUND_SONICVIBES is not set -# CONFIG_SOUND_TRIDENT is not set -# CONFIG_SOUND_MSNDCLAS is not set -# CONFIG_SOUND_MSNDPIN is not set -# CONFIG_SOUND_VIA82CXXX is not set -# CONFIG_MIDI_VIA82CXXX is not set -# CONFIG_SOUND_OSS is not set -# CONFIG_SOUND_TVMIXER is not set +# CONFIG_SOUND is not set # # USB support # -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_BANDWIDTH is not set -# CONFIG_USB_LONG_TIMEOUT is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_EHCI_HCD is not set -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -CONFIG_USB_OHCI=y - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_MIDI is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m - -# -# USB Human Interface Devices (HID) -# -CONFIG_USB_HID=y -CONFIG_USB_HIDINPUT=y -# CONFIG_USB_HIDDEV is not set -# CONFIG_USB_AIPTEK is not set -# CONFIG_USB_WACOM is not set - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -CONFIG_USB_SCANNER=m -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -CONFIG_USB_SERIAL=m -# CONFIG_USB_SERIAL_DEBUG is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -CONFIG_USB_SERIAL_VISOR=m -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_AUERSWALD is not set -# CONFIG_USB_TIGL is not set -# CONFIG_USB_BRLVGER is not set -# CONFIG_USB_LCD is not set +# CONFIG_USB is not set # # Bluetooth support @@ -1034,12 +452,4 @@ # # Kernel hacking # -CONFIG_DEBUG_KERNEL=y -CONFIG_MAGIC_SYSRQ=y -# CONFIG_DEBUG_HIGHMEM is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_WAITQ is not set -# CONFIG_KGDB is not set -CONFIG_XMON=y -# CONFIG_BDI_SWITCH is not set -# CONFIG_MORE_COMPILE_OPTIONS is not set +# CONFIG_DEBUG_KERNEL is not set diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/Makefile cset-v2.4.20/arch/ppc/kernel/Makefile --- cset-v2.4.20~/arch/ppc/kernel/Makefile 2004-10-25 15:06:01.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/Makefile 2004-11-02 17:39:37.000000000 +0900 @@ -25,14 +25,15 @@ # Start off with 'head.o', change as needed. HEAD-y := head.o HEAD-$(CONFIG_6xx) += idle_6xx.o -HEAD-$(CONFIG_4xx) := head_4xx.o +HEAD-$(CONFIG_40x) := head_4xx.o +HEAD-$(CONFIG_44x) := head_44x.o HEAD-$(CONFIG_8xx) := head_8xx.o all: $(HEAD-y) kernel.o O_TARGET := kernel.o -export-objs := ppc_ksyms.o time.o +export-objs := ppc_ksyms.o time.o ocp.o obj-y := entry.o traps.o irq.o idle.o time.o misc.o \ process.o signal.o ptrace.o align.o \ @@ -45,7 +46,15 @@ obj-$(CONFIG_KGDB) += ppc-stub.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_TAU) += temp.o -obj-$(CONFIG_4xx) += ppc4xx_pic.o +obj-$(CONFIG_40x) += ppc4xx_setup.o ppc4xx_pic.o +obj-$(CONFIG_4xx) += ocp.o todc_time.o +ifeq ($(CONFIG_PCI),y) +obj-$(CONFIG_40x) += ppc405_pci.o +obj-$(CONFIG_4xx) += indirect_pci.o pci_auto.o +endif +obj-$(CONFIG_44x) += ppc4xx_pic.o ibm44x_common.o +obj-$(CONFIG_440GX) += ibm440gx_common.o +obj-$(CONFIG_440GP) += ibm440gp_common.o obj-$(CONFIG_8xx) += m8xx_setup.o ppc8xx_pic.o ifeq ($(CONFIG_8xx),y) obj-$(CONFIG_PCI) += qspan_pci.o @@ -69,6 +78,7 @@ l2cr.o: l2cr.S ppc_defs.h head.o: head.S ppc_defs.h head_4xx.o: head_4xx.S ppc_defs.h +head_44x.o: head_44x.S ppc_defs.h head_8xx.o: head_8xx.S ppc_defs.h idle_6xx.o: idle_6xx.S ppc_defs.h diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/cputable.c cset-v2.4.20/arch/ppc/kernel/cputable.c --- cset-v2.4.20~/arch/ppc/kernel/cputable.c 2004-10-25 15:04:54.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/cputable.c 2004-11-02 17:38:17.000000000 +0900 @@ -308,7 +308,7 @@ __setup_cpu_8xx /* Empty */ }, #endif /* CONFIG_8xx */ -#ifdef CONFIG_4xx +#ifdef CONFIG_40x { /* 403GC */ 0xffffff00, 0x00200200, "403GC", CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, @@ -345,6 +345,36 @@ 0, /*__setup_cpu_405 */ }, #endif /* CONFIG_4xx */ +#ifdef CONFIG_44x + { /* 440GP Rev. B */ + 0xf0000fff, 0x40000440, "440GP Rev. B", + CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, + PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, + 32, 32, + 0, /*__setup_cpu_440 */ + }, + { /* 440GP Rev. C */ + 0xf0000fff, 0x40000481, "440GP Rev. C", + CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, + PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, + 32, 32, + 0, /*__setup_cpu_440 */ + }, + { /* 440GX Rev. A */ + 0xf0000fff, 0x50000850, "440GX Rev. A", + CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, + PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, + 32, 32, + 0, /*__setup_cpu_440 */ + }, + { /* 440GX Rev. B */ + 0xf0000fff, 0x50000851, "440GX Rev. B", + CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, + PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, + 32, 32, + 0, /*__setup_cpu_440 */ + }, +#endif /* CONFIG_44x */ #if !CLASSIC_PPC { /* default match */ 0x00000000, 0x00000000, "(generic PPC)", diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/entry.S cset-v2.4.20/arch/ppc/kernel/entry.S --- cset-v2.4.20~/arch/ppc/kernel/entry.S 2004-10-25 15:02:44.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/entry.S 2004-11-01 22:35:09.000000000 +0900 @@ -311,6 +311,9 @@ */ mfmsr r0 /* Get current interrupt state */ rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */ +#ifdef CONFIG_4xx + rlwinm r0,r0,0,23,21 /* clear MSR_DE in r0 */ +#endif SYNC /* Some chip revs have problems here... */ mtmsr r0 /* Update machine state */ @@ -326,6 +329,14 @@ mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) #endif /* CONFIG_ALTIVEC */ +#if defined(CONFIG_4xx) && !defined(CONFIG_BDI_SWITCH) + /* Restore the processor debugging state of the thread. Only do + * this if we aren't using an Abatron BDI JTAG debugger. It doesn't + * tolerate others mucking with the debug registers. + */ + lwz r0,THREAD+THREAD_DBCR0(r2) + mtspr SPRN_DBCR0,r0 +#endif addi r0,r1,INT_FRAME_SIZE /* size of frame */ stw r0,THREAD+KSP(r2) /* save kernel stack pointer */ tophys(r8,r1) diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/head_44x.S cset-v2.4.20/arch/ppc/kernel/head_44x.S --- cset-v2.4.20~/arch/ppc/kernel/head_44x.S 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/head_44x.S 2004-11-02 17:38:17.000000000 +0900 @@ -0,0 +1,1102 @@ +/* + * arch/ppc/kernel/head_44x.S + * + * Kernel execution entry point code. + * + * Matt Porter + * + * Copyright 2002-2003 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "ppc_defs.h" + +/* + * Preprocessor Defines + */ + +#define STND_EXC 0 +#define CRIT_EXC 1 + +#ifdef CONFIG_440A +#define MCHK_EXC 2 +#define __SPRN_MCSRR0 SPRN_MCSRR0 +#define __SPRN_MCSRR1 SPRN_MCSRR1 +#else +#define MCHK_EXC CRIT_EXC +#define __SPRN_MCSRR0 SPRN_CSRR0 +#define __SPRN_MCSRR1 SPRN_CSRR1 +#endif + +/* + * Macros + */ + +#define SET_IVOR(vector_number, vector_label) \ + li r26,vector_label@l; \ + mtspr SPRN_IVOR##vector_number,r26; \ + sync + +/* As with the other PowerPC ports, it is expected that when code + * execution begins here, the following registers contain valid, yet + * optional, information: + * + * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) + * r4 - Starting address of the init RAM disk + * r5 - Ending address of the init RAM disk + * r6 - Start of kernel command line string (e.g. "mem=128") + * r7 - End of kernel command line string + * + */ + .text +_GLOBAL(_stext) +_GLOBAL(_start) + /* + * Reserve a word at a fixed location to store the address + * of abatron_pteptrs + */ + nop + +/* + * Save parameters we are passed + */ + mr r31,r3 + mr r30,r4 + mr r29,r5 + mr r28,r6 + mr r27,r7 + li r24,0 /* CPU number */ + +/* + * Set up the initial MMU state + * + * We are still executing code at the virtual address + * mappings set by the firmware for the base of RAM. + * + * We first invalidate all TLB entries but the one + * we are running from. We then load the KERNELBASE + * mappings so we can begin to use kernel addresses + * natively and so the interrupt vector locations are + * permanently pinned (necessary since Book E + * implementations always have translation enabled). + * + * TODO: Use the known TLB entry we are running from to + * determine which physical region we are located + * in. This can be used to determine where in RAM + * (on a shared CPU system) or PCI memory space + * (on a DRAMless system) we are located. + * For now, we assume a perfect world which means + * we are located at the base of DRAM (physical 0). + */ + +/* + * Search TLB for entry that we are currently using. + * Invalidate all entries but the one we are using. + */ + /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */ + mfspr r3,SPRN_MMUCR /* Get MMUCR */ + lis r4,PPC44x_MMUCR_STS@h + ori r4,r4,PPC44x_MMUCR_TID@l /* Create mask */ + andc r3,r3,r4 /* Clear out TID/STS bits */ + mfspr r4,SPRN_PID /* Get PID */ + or r3,r3,r4 /* Set TID bits */ + mfmsr r5 /* Get MSR */ + andi. r5,r5,MSR_IS@l /* TS=1? */ + beq wmmucr /* If not, leave STS=0 */ + oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */ +wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */ + sync + + bl invstr /* Find our address */ +invstr: mflr r5 /* Make it accessible */ + tlbsx r23,0,r5 /* Find entry we are in */ + li r4,0 /* Start at TLB entry 0 */ + li r3,0 /* Set PAGEID inval value */ +1: cmpw r23,r4 /* Is this our entry? */ + beq skpinv /* If so, skip the inval */ + tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */ +skpinv: addi r4,r4,1 /* Increment */ + cmpwi r4,64 /* Are we done? */ + bne 1b /* If not, repeat */ + isync /* If so, context change */ + +/* + * Configure and load pinned entries into TLB slots 62 and 63. + */ + + lis r3,KERNELBASE@h /* Load the kernel virtual address */ + ori r3,r3,KERNELBASE@l + + /* Kernel is at the base of RAM */ + li r4, 0 /* Load the kernel physical address */ + + /* Load the kernel PID = 0 */ + li r0,0 + mtspr SPRN_PID,r0 + sync + + /* Load the kernel TID = 0 */ + mfspr r5,SPRN_MMUCR + lis r6, PPC44x_MMUCR_TID@h + ori r6,r6,PPC44x_MMUCR_TID@l + andc r5,r5,r6 + mtspr SPRN_MMUCR,r5 + sync + + /* pageid fields */ + clrrwi r3,r3,10 /* Mask off the effective page number */ + ori r3,r3,(PPC44x_TLB_VALID | PPC44x_TLB_PAGESZ(PPC44x_PAGESZ_256M)) + + /* xlat fields */ + clrrwi r4,r4,10 /* Mask off the real page number */ + /* ERPN is 0 for first 4GB page */ + + /* attrib fields */ + /* Added guarded bit to protect against speculative loads/stores */ + li r5,0 + ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G) + + li r0,62 /* TLB slot 62 */ + + tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ + tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ + tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ + + /* Force context change */ + mfmsr r0 + mtspr SRR1, r0 + lis r0,3f@h + ori r0,r0,3f@l + mtspr SRR0,r0 + sync + rfi + + /* If necessary, invalidate original entry we used */ +3: cmpwi r23,62 + beq 4f + li r6,0 + tlbwe r6,r23,PPC44x_TLB_PAGEID + sync + +4: ori r3,r3,PPC44x_TLB_TS /* TS = 1 */ + + li r0,63 /* TLB slot 63 */ + + tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ + tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ + tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ + +#ifdef CONFIG_SERIAL_TEXT_DEBUG + /* + * Add temporary UART mapping for early debug. This + * mapping must be identical to that used by the early + * bootloader code since the same asm/serial.h parameters + * are used for polled operation. + */ + /* pageid fields */ + lis r3,0xe000 + ori r3,r3,(PPC44x_TLB_VALID | PPC44x_TLB_PAGESZ(PPC44x_PAGESZ_256M)) + + /* xlat fields */ + lis r4,0x4000 /* RPN is 0x40000000 */ + ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */ + + /* attrib fields */ + li r5,0 + ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_I | PPC44x_TLB_G) + + li r0,60 /* TLB slot 60 */ + + tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ + tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ + tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ + + ori r3,r3,PPC44x_TLB_TS /* Translation state 1 */ + + li r0,61 /* TLB slot 61 */ + + tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ + tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ + tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ +#endif /* CONFIG_SERIAL_TEXT_DEBUG */ + + /* Force context change */ + isync + + /* Establish the interrupt vector offsets */ + SET_IVOR(0, CriticalInput); + SET_IVOR(1, MachineCheck); + SET_IVOR(2, DataStorage); + SET_IVOR(3, InstructionStorage); + SET_IVOR(4, ExternalInput); + SET_IVOR(5, Alignment); + SET_IVOR(6, Program); + SET_IVOR(7, FloatingPointUnavailable); + SET_IVOR(8, SystemCall); + SET_IVOR(9, AuxillaryProcessorUnavailable); + SET_IVOR(10, Decrementer); + SET_IVOR(11, FixedIntervalTimer); + SET_IVOR(12, WatchdogTimer); + SET_IVOR(13, DataTLBError); + SET_IVOR(14, InstructionTLBError); + SET_IVOR(15, Debug); + + /* Establish the interrupt vector base */ + lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ + mtspr SPRN_IVPR,r4 + + /* + * This is where the main kernel code starts. + */ + + /* ptr to current */ + lis r2,init_task_union@h + ori r2,r2,init_task_union@l + + /* ptr to current thread */ + addi r4,r2,THREAD /* init task's THREAD */ + mtspr SPRG3,r4 + li r3,0 + mtspr SPRG2,r3 /* 0 => r1 has kernel sp */ + + /* stack */ + addi r1,r2,TASK_UNION_SIZE + li r0,0 + stwu r0,-STACK_FRAME_OVERHEAD(r1) + + bl early_init + +/* + * Decide what sort of machine this is and initialize the MMU. + */ + mr r3,r31 + mr r4,r30 + mr r5,r29 + mr r6,r28 + mr r7,r27 + bl machine_init + bl MMU_init + + /* Setup PTE pointers for the Abatron bdiGDB */ + lis r6, swapper_pg_dir@h + ori r6, r6, swapper_pg_dir@l + lis r5, abatron_pteptrs@h + ori r5, r5, abatron_pteptrs@l + lis r4, KERNELBASE@h + ori r4, r4, KERNELBASE@l + stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ + stw r6, 0(r5) + + /* Let's move on */ + lis r4,start_kernel@h + ori r4,r4,start_kernel@l + lis r3,MSR_KERNEL@h + ori r3,r3,MSR_KERNEL@l + mtspr SRR0,r4 + mtspr SRR1,r3 + rfi /* change context and jump to start_kernel */ + +/* + * Interrupt vector entry code + * + * The Book E MMUs are always on so we don't need to handle + * interrupts in real mode as with previous PPC processors. In + * this case we handle interrupts in the kernel virtual address + * space. + * + * Interrupt vectors are dynamically placed relative to the + * interrupt prefix as determined by the address of interrupt_base. + * The interrupt vectors offsets are programmed using the labels + * for each interrupt vector entry. + * + * Interrupt vectors must be aligned on a 16 byte boundary. + * We align on a 32 byte cache line boundary for good measure. + */ + +#define COMMON_PROLOG \ +0: mtspr SPRN_SPRG0,r20; /* We need r20, move it to SPRG0 */\ + mtspr SPRN_SPRG1,r21; /* We need r21, move it to SPRG1 */\ + mfcr r20; /* We need the CR, move it to r20 */\ + mfspr r21,SPRN_SPRG2; /* Exception stack to use */\ + cmpwi cr0,r21,0; /* From user mode or RTAS? */\ + bne 1f; /* Not RTAS, branch */\ + mr r21, r1; /* Move vka in r1 to r21 */\ + subi r21,r21,INT_FRAME_SIZE; /* Allocate an exception frame */\ +1: stw r20,_CCR(r21); /* Save CR on the stack */\ + stw r22,GPR22(r21); /* Save r22 on the stack */\ + stw r23,GPR23(r21); /* r23 Save on the stack */\ + mfspr r20,SPRN_SPRG0; /* Get r20 back out of SPRG0 */\ + stw r20,GPR20(r21); /* Save r20 on the stack */\ + mfspr r22,SPRN_SPRG1; /* Get r21 back out of SPRG0 */\ + stw r22,GPR21(r21); /* Save r21 on the stack */\ + mflr r20; \ + stw r20,_LINK(r21); /* Save LR on the stack */\ + mfctr r22; \ + stw r22,_CTR(r21); /* Save CTR on the stack */\ + mfspr r20,XER; \ + stw r20,_XER(r21); /* Save XER on the stack */ + +#define COMMON_EPILOG \ + stw r0,GPR0(r21); /* Save r0 on the stack */\ + stw r1,GPR1(r21); /* Save r1 on the stack */\ + stw r2,GPR2(r21); /* Save r2 on the stack */\ + stw r1,0(r21); \ + mr r1,r21; /* Set-up new kernel stack pointer */\ + SAVE_4GPRS(3, r21); /* Save r3 through r6 on the stack */\ + SAVE_GPR(7, r21); /* Save r7 on the stack */ + +#define STND_EXCEPTION_PROLOG \ + COMMON_PROLOG; \ + mfspr r22,SPRN_SRR0; /* Faulting instruction address */\ + lis r20,MSR_WE@h; \ + mfspr r23,SPRN_SRR1; /* MSR at the time of fault */\ + andc r23,r23,r20; /* disable processor wait state */\ + COMMON_EPILOG; + +#define CRIT_EXCEPTION_PROLOG \ + COMMON_PROLOG; \ + mfspr r22,SPRN_CSRR0; /* Faulting instruction address */\ + lis r20,MSR_WE@h; \ + mfspr r23,SPRN_CSRR1; /* MSR at the time of fault */\ + andc r23,r23,r20; /* disable processor wait state */\ + COMMON_EPILOG; + +#define START_EXCEPTION(label) \ + .align 5; \ +label: + +#define FINISH_EXCEPTION(n, func) \ + bl transfer_to_handler; \ + .long func; \ + .long ret_from_except; \ + .long n + +#define STND_EXCEPTION(n, label, func) \ + START_EXCEPTION(label) \ + STND_EXCEPTION_PROLOG; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + li r7,STND_EXC; \ + li r20,MSR_KERNEL; \ + FINISH_EXCEPTION(n, func) + +#define CRIT_EXCEPTION(n, label, func) \ + START_EXCEPTION(label) \ + CRIT_EXCEPTION_PROLOG; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + li r7,CRIT_EXC; \ + li r20,MSR_KERNEL; \ + FINISH_EXCEPTION(n, func) + +interrupt_base: + + /* Critical Input Interrupt */ + CRIT_EXCEPTION(0x100, CriticalInput,UnknownException); + + /* Machine Check Interrupt */ + /* TODO: provide bus error register status */ + START_EXCEPTION(MachineCheck) + COMMON_PROLOG; + mfspr r22,__SPRN_MCSRR0 /* Faulting instruction address */ + lis r20,MSR_WE@h + mfspr r23,__SPRN_MCSRR1 /* MSR at the time of fault */ + andc r23,r23,r20 /* disable processor wait state */ + COMMON_EPILOG; +#ifdef CONFIG_440A + lis r20,MCSR_MCS@h + mfspr r4,SPRN_MCSR /* We may want to access original + MCSR as arg2 in the future. --ebs */ + mtspr SPRN_MCSR,r20 /* Clear Machine Check Summary field */ +#endif + mfspr r5,SPRN_ESR /* Grab the ESR, save it */ + stw r5,_ESR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r7,MCHK_EXC + li r20,MSR_KERNEL + FINISH_EXCEPTION(0x200, MachineCheckException) + + /* Data Storage Interrupt */ + START_EXCEPTION(DataStorage) + mtspr SPRG0, r20 /* Save some working registers */ + mtspr SPRG1, r21 + mtspr SPRG4W, r22 + mtspr SPRG5W, r23 + mtspr SPRG6W, r24 + mfcr r21 + mtspr SPRG7W, r21 + + /* + * Check if it was a store fault, if not then bail + * because a user tried to access a kernel or + * read-protected page. Otherwise, get the + * offending address and handle it. + */ + mfspr r20, SPRN_ESR + andis. r20, r20, ESR_DST@h + beq 2f + + mfspr r20, SPRN_DEAR /* Get faulting address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + andis. r21, r20, 0x8000 + beq 3f + lis r21, swapper_pg_dir@h + ori r21, r21, swapper_pg_dir@l + + mfspr r22,SPRN_MMUCR /* Set TID to 0 */ + li r23,PPC44x_MMUCR_TID@l + andc r22,r22,r23 + mtspr SPRN_MMUCR,r22 + + b 4f + + /* Get the PGD for the current thread */ +3: + mfspr r21,SPRG3 + lwz r21,PGDIR(r21) + + /* Load MMUCR with our PID and STS= */ + mfspr r22,SPRN_MMUCR /* Get MMUCR */ + lis r23,PPC44x_MMUCR_STS@h + ori r23,r23,PPC44x_MMUCR_TID@l /* Create mask */ + andc r22,r22,r23 /* Clear out TID/STS bits */ + mfspr r23,SPRN_PID /* Get PID */ + or r22,r22,r23 /* Set TID bits */ + mfspr r24,SPRN_SRR1 /* Get SRR1 */ + andi. r24,r24,MSR_IS@l /* TS=1? */ + beq 4f /* If not, leave STS=0 */ + oris r22,r22,PPC44x_MMUCR_STS@h /* Set STS=1 */ + mtspr SPRN_MMUCR,r22 +4: + rlwinm r22, r20, 13, 19, 29 /* Compute pgdir/pmd offset */ + lwzx r21, r22, r21 /* Get pgd/pmd entry */ + rlwinm. r22, r21, 0, 0, 20 /* Extract pt base address */ + beq 2f /* Bail if no table */ + + rlwimi r22, r20, 23, 20, 28 /* Compute pte address */ + lwz r21, 4(r22) /* Get pte entry */ + + andi. r23, r21, _PAGE_RW /* Is it writeable? */ + beq 2f /* Bail if not */ + + /* Update 'changed'. + */ + ori r21, r21, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE + stw r21, 4(r22) /* Update Linux page table */ + + /* FIXME: Staticly setting some permissions */ + li r23, 0x003f /* Set UX,UW,UR,SX,SW,SR */ + andi. r21,r21,0xffff /* Clear MS 16 bits */ + /* FIXME: Force attributes */ + ori r21,r21, 0x0100 /* Set G */ + /* FIXME: Already set in PTE */ + rlwimi r21,r23,0,26,31 /* Insert static perms */ + + lis r23,0xffff + ori r23,r23,0x0fff /* Set U0-U3 mask */ + and r21,r21,r23 /* Clear U0-U3 */ + + /* find the TLB index that caused the fault. It has to be here. */ + tlbsx r24, 0, r20 + + tlbwe r21, r24, PPC44x_TLB_ATTRIB /* Write ATTRIB */ + + /* Done...restore registers and get out of here. + */ + mfspr r21, SPRG7R + mtcr r21 + mfspr r24, SPRG6R + mfspr r23, SPRG5R + mfspr r22, SPRG4R + + mfspr r21, SPRG1 + mfspr r20, SPRG0 + rfi /* Force context change */ + +2: + /* + * The bailout. Restore registers to pre-exception conditions + * and call the heavyweights to help us out. + */ + mfspr r21, SPRG7R + mtcr r21 + mfspr r24, SPRG6R + mfspr r23, SPRG5R + mfspr r22, SPRG4R + + mfspr r21, SPRG1 + mfspr r20, SPRG0 + b data_access + + /* Instruction Storage Interrupt */ + START_EXCEPTION(InstructionStorage) + STND_EXCEPTION_PROLOG + mfspr r5,SPRN_ESR /* Grab the ESR, save it */ + stw r5,_ESR(r21) + mr r4,r22 /* Pass SRR0 as arg2 */ + li r5,0 /* Pass zero as arg3 */ + addi r3,r1,STACK_FRAME_OVERHEAD + li r7,STND_EXC + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* Copy EE bit from the saved MSR */ + FINISH_EXCEPTION(0x400, do_page_fault)/* do_page_fault(regs, SRR0, SRR1) */ + + /* External Input Interrupt */ + START_EXCEPTION(ExternalInput) + STND_EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + li r7,STND_EXC + li r20,MSR_KERNEL + li r4,0 + bl transfer_to_handler +_GLOBAL(do_IRQ_intercept) + .long do_IRQ + .long ret_from_intercept + .long 0x500 + + /* Alignment Interrupt */ + START_EXCEPTION(Alignment) + STND_EXCEPTION_PROLOG + mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */ + stw r4,_DEAR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r7,STND_EXC + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* Copy EE bit from the saved MSR */ + FINISH_EXCEPTION(0x600, AlignmentException) + + /* Program Interrupt */ + START_EXCEPTION(Program) + STND_EXCEPTION_PROLOG + mfspr r4,SPRN_ESR /* Grab the ESR, save it */ + stw r4,_ESR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r7,STND_EXC + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* Copy EE bit from the saved MSR */ + FINISH_EXCEPTION(0x700, ProgramCheckException) + + /* Floating Point Unavailable Interrupt */ + STND_EXCEPTION(0x2010, FloatingPointUnavailable,UnknownException); + + /* System Call Interrupt */ + START_EXCEPTION(SystemCall) + STND_EXCEPTION_PROLOG + stw r3,ORIG_GPR3(r21) + li r7,STND_EXC + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* Copy EE bit from the saved MSR */ + FINISH_EXCEPTION(0xc00, DoSyscall) + + /* Auxillary Processor Unavailable */ + STND_EXCEPTION(0x2020, AuxillaryProcessorUnavailable,UnknownException); + + /* Decrementer Interrupt */ + START_EXCEPTION(Decrementer) + STND_EXCEPTION_PROLOG + lis r0,TSR_DIS@h /* Setup the DEC interrupt mask */ + mtspr SPRN_TSR,r0 /* Clear the DEC interrupt */ + addi r3,r1,STACK_FRAME_OVERHEAD + li r7,STND_EXC + li r20,MSR_KERNEL + bl transfer_to_handler +_GLOBAL(timer_interrupt_intercept) + .long timer_interrupt + .long ret_from_intercept + .long 0x1000 + + /* Fixed Internal Timer Interrupt */ + /* TODO: Add FIT support */ + STND_EXCEPTION(0x1010, FixedIntervalTimer,UnknownException); + + /* Watchdog Timer Interrupt */ + /* TODO: Add watchdog support */ + CRIT_EXCEPTION(0x1020, WatchdogTimer,UnknownException); + + /* Data TLB Error Interrupt */ + START_EXCEPTION(DataTLBError) + mtspr SPRG0, r20 /* Save some working registers */ + mtspr SPRG1, r21 + mtspr SPRG4W, r22 + mtspr SPRG5W, r23 + mtspr SPRG6W, r24 + mfcr r21 + mtspr SPRG7W, r21 + mfspr r20, SPRN_DEAR /* Get faulting address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + andis. r21, r20, 0x8000 + beq 3f + lis r21, swapper_pg_dir@h + ori r21, r21, swapper_pg_dir@l + + mfspr r22,SPRN_MMUCR /* Set TID to 0 */ + li r23,PPC44x_MMUCR_TID@l + andc r22,r22,r23 + mtspr SPRN_MMUCR,r22 + + b 4f + + /* Get the PGD for the current thread */ +3: + mfspr r21,SPRG3 + lwz r21,PGDIR(r21) + + /* Load PID into MMUCR TID */ + li r23,PPC44x_MMUCR_TID@l /* Create mask */ + andc r22,r22,r23 /* Clear out TID/STS bits */ + mfspr r23,SPRN_PID /* Get PID */ + or r22,r22,r23 + mtspr SPRN_MMUCR,r22 +4: + rlwinm r22, r20, 13, 19, 29 /* Compute pgdir/pmd offset */ + lwzx r21, r22, r21 /* Get pgd/pmd entry */ + rlwinm. r22, r21, 0, 0, 20 /* Extract pt base address */ + beq 2f /* Bail if no table */ + + rlwimi r22, r20, 23, 20, 28 /* Compute pte address */ + lwz r21, 4(r22) /* Get pte entry */ + andi. r23, r21, _PAGE_PRESENT /* Is the page present? */ + beq 2f /* Bail if not present */ + + ori r21, r21, _PAGE_ACCESSED + stw r21, 4(r22) + + /* Jump to common tlb load */ + b finish_tlb_load + +2: + /* The bailout. Restore registers to pre-exception conditions + * and call the heavyweights to help us out. + */ + mfspr r21, SPRG7R + mtcr r21 + mfspr r24, SPRG6R + mfspr r23, SPRG5R + mfspr r22, SPRG4R + mfspr r21, SPRG1 + mfspr r20, SPRG0 + b data_access + + /* Instruction TLB Error Interrupt */ + /* + * Nearly the same as above, except we get our + * information from different registers and bailout + * to a different point. + */ + START_EXCEPTION(InstructionTLBError) + mtspr SPRG0, r20 /* Save some working registers */ + mtspr SPRG1, r21 + mtspr SPRG4W, r22 + mtspr SPRG5W, r23 + mtspr SPRG6W, r24 + mfcr r21 + mtspr SPRG7W, r21 + mfspr r20, SRR0 /* Get faulting address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + andis. r21, r20, 0x8000 + beq 3f + lis r21, swapper_pg_dir@h + ori r21, r21, swapper_pg_dir@l + + mfspr r22,SPRN_MMUCR /* Set TID to 0 */ + li r23,PPC44x_MMUCR_TID@l + andc r22,r22,r23 + mtspr SPRN_MMUCR,r22 + + b 4f + + /* Get the PGD for the current thread */ +3: + mfspr r21,SPRG3 + lwz r21,PGDIR(r21) + + /* Load PID into MMUCR TID */ + li r23,PPC44x_MMUCR_TID@l /* Create mask */ + andc r22,r23,r23 /* Clear out TID/STS bits */ + mfspr r23,SPRN_PID /* Get PID */ + or r22,r22,r23 + mtspr SPRN_MMUCR,r22 + +4: + rlwinm r22, r20, 13, 19, 29 /* Compute pgdir/pmd offset */ + lwzx r21, r22, r21 /* Get pgd/pmd entry */ + rlwinm. r22, r21, 0, 0, 20 /* Extract pt base address */ + beq 2f /* Bail if no table */ + + rlwimi r22, r20, 23, 20, 28 /* Compute pte address */ + lwz r21, 4(r22) /* Get pte entry */ + andi. r23, r21, _PAGE_PRESENT /* Is the page present? */ + beq 2f /* Bail if not present */ + + ori r21, r21, _PAGE_ACCESSED + stw r21, 4(r22) + + /* Jump to common TLB load point */ + b finish_tlb_load + +2: + /* The bailout. Restore registers to pre-exception conditions + * and call the heavyweights to help us out. + */ + mfspr r21, SPRG7R + mtcr r21 + mfspr r24, SPRG6R + mfspr r23, SPRG5R + mfspr r22, SPRG4R + mfspr r21, SPRG1 + mfspr r20, SPRG0 + b InstructionStorage + +/* Check for a single step debug exception while in an exception + * handler before state has been saved. This is to catch the case + * where an instruction that we are trying to single step causes + * an exception (eg ITLB/DTLB miss) and thus the first instruction of + * the exception handler generates a single step debug exception. + * + * If we get a debug trap on the first instruction of an exception handler, + * we reset the MSR_DE in the _exception handlers_ MSR (the debug trap is + * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). + * The exception handler was handling a non-critical interrupt, so it will + * save (and later restore) the MSR via SPRN_SRR1, which will still have + * the MSR_DE bit set. + */ + /* Debug Interrupt */ + START_EXCEPTION(Debug) + /* This first instruction was already executed by the exception + * handler and must be the first instruction of every exception + * handler. + */ + mtspr SPRN_SPRG0,r20 /* Save some working registers... */ + mtspr SPRN_SPRG1,r21 + mtspr SPRN_SPRG4W,r22 + mfcr r20 /* ..and the cr because we change it */ + + mfspr r21,SPRN_CSRR1 /* MSR at the time of fault */ + andi. r21,r21,MSR_PR + bne+ 2f /* trapped from problem state */ + + mfspr r21,SPRN_CSRR0 /* Faulting instruction address */ + lis r22, KERNELBASE@h + ori r22, r22, KERNELBASE@l + cmplw r21,r22 + blt+ 2f /* addr below exception vectors */ + + lis r22, Debug@h + ori r22, r22, Debug@l + cmplw r21,r22 + bgt+ 2f /* addr above TLB exception vectors */ + + lis r21,DBSR_IC@h /* Remove the trap status */ + mtspr SPRN_DBSR,r21 + + mfspr r21,SPRN_CSRR1 + rlwinm r21,r21,0,23,21 /* clear MSR_DE */ + mtspr SPRN_CSRR1, r21 /* restore MSR at rcfi without DE */ + + mtcrf 0xff,r20 /* restore registers */ + mfspr r22,SPRN_SPRG4R + mfspr r21,SPRN_SPRG1 + mfspr r20,SPRN_SPRG0 + + sync + rfci /* return to the exception handler */ + b . /* prevent prefetch past rfci */ + +2: + mtcrf 0xff,r20 /* restore registers */ + mfspr r22,SPRN_SPRG4R + mfspr r21,SPRN_SPRG1 + mfspr r20,SPRN_SPRG0 + + CRIT_EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + li r7,CRIT_EXC; + li r20,MSR_KERNEL + FINISH_EXCEPTION(0x2000, DebugException) + +/* + * Local functions + */ + + /* + * Data TLB exceptions will bail out to this point + * if they can't resolve the lightweight TLB fault. + */ +data_access: + STND_EXCEPTION_PROLOG + mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ + stw r5,_ESR(r21) + mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ + stw r4,_DEAR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r7,STND_EXC + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* Copy EE bit from the saved MSR */ + FINISH_EXCEPTION(0x800, do_page_fault) /* do_page_fault(regs, ESR, DEAR) */ + +/* + * Both the instruction and data TLB miss get to this + * point to load the TLB. + * r20 - EA of fault + * r21 - available to use + * r22 - Pointer to the 64-bit PTE + * r23 - available to use + * r24 - available to use + * MMUCR - loaded with proper value when we get here + * Upon exit, we reload everything and RFI. + */ +finish_tlb_load: + /* + * We set execute, because we don't have the granularity to + * properly set this at the page level (Linux problem). + * If shared is set, we cause a zero PID->TID load. + * Many of these bits are software only. Bits we don't set + * here we (properly should) assume have the appropriate value. + */ + + /* Load the next available TLB index */ + lis r23, tlb_44x_index@h + ori r23, r23, tlb_44x_index@l + lwz r24, 0(r23) + /* Load the TLB high watermark */ + lis r23, tlb_44x_hwater@h + ori r23, r23, tlb_44x_hwater@l + lwz r21, 0(r23) + + + /* Increment, rollover, and store TLB index */ + addi r24, r24, 1 + cmpw 0, r24, r21 /* reserve entries 62-63 for kernel */ + ble 7f + li r24, 0 +7: + /* Load the next available TLB index */ + lis r23, tlb_44x_index@h + ori r23, r23, tlb_44x_index@l + stw r24, 0(r23) + +6: + lwz r23, 0(r22) /* Get MS word of PTE */ + lwz r21, 4(r22) /* Get LS word of PTE */ + rlwimi r23, r21, 0, 0 , 19 /* Insert RPN */ + tlbwe r23, r24, PPC44x_TLB_XLAT /* Write XLAT */ + + /* + * Create PAGEID. This is the faulting address plus + * a set of static bits. The static bits are page + * size and valid. Bits 20 and 21 should be zero + * for a page size of 4KB. + */ + li r22, 0x0210 /* Set size and valid */ + mfspr r23, SPRN_SRR1 /* Get SRR1 */ + andi. r23, r23, MSR_IS@l + beq 7f + ori r22, r22, PPC44x_TLB_TS@l /* Set TS=1 */ +7: rlwimi r20, r22, 0, 20, 31 /* Insert statics */ + tlbwe r20, r24, PPC44x_TLB_PAGEID /* Write PAGEID */ + + /* FIXME: Staticly setting some permissions */ + li r23, 0x002d /* Set UX,UR,SX,SR */ + andi. r21, r21, 0xffff /* Clear MS 16 bits */ + andi. r22, r21, 0x0002 /* _PAGE_HWWRITE? */ + beq 8f + ori r23, r23, 0x0002 /* Set SW */ + /* FIXME: Force attributes */ +8: ori r21, r21, 0x0100 /* Set G */ + /* FIXME: Already set in PTE */ + rlwimi r21, r23, 0, 26, 31 /* Insert static perms */ + + lis r23,0xffff + ori r23,r23,0x0fff /* Set U0-U3 mask */ + and r21,r21,r23 /* Clear U0-U3 */ + tlbwe r21, r24, PPC44x_TLB_ATTRIB /* Write ATTRIB */ + + /* Done...restore registers and get out of here. + */ + mfspr r21, SPRG7R + mtcr r21 + mfspr r24, SPRG6R + mfspr r23, SPRG5R + mfspr r22, SPRG4R + mfspr r21, SPRG1 + mfspr r20, SPRG0 + rfi /* Force context change */ + +/* + * Global functions + */ + +/* + * extern void giveup_altivec(struct task_struct *prev) + * + * The 44x core does not have an AltiVec unit. + */ +_GLOBAL(giveup_altivec) + blr + +/* + * extern void giveup_fpu(struct task_struct *prev) + * + * The 44x core does not have an FPU. + */ +_GLOBAL(giveup_fpu) + blr + +/* + * extern void abort(void) + * + * At present, this routine just applies a system reset. + */ +_GLOBAL(abort) + mfspr r13,SPRN_DBCR0 + oris r13,r13,DBCR_RST(DBCR_RST_SYSTEM)@h + mtspr SPRN_DBCR0,r13 + +_GLOBAL(set_context) + +#ifdef CONFIG_BDI_SWITCH + /* Context switch the PTE pointer for the Abatron BDI2000. + * The PGDIR is the second parameter. + */ + lis r5, abatron_pteptrs@h + ori r5, r5, abatron_pteptrs@l + stw r4, 0x4(r5) +#endif + mtspr SPRN_PID,r3 + isync /* Force context change */ + blr + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception, turning + * on address translation. + */ +_GLOBAL(transfer_to_handler) + stw r22,_NIP(r21) /* Save the faulting IP on the stack */ + stw r23,_MSR(r21) /* Save the exception MSR on stack */ + SAVE_4GPRS(8, r21) /* Save r8 through r11 on the stack */ + SAVE_8GPRS(12, r21) /* Save r12 through r19 on the stack */ + SAVE_8GPRS(24, r21) /* Save r24 through r31 on the stack */ + andi. r23,r23,MSR_PR /* Is this from user space? */ + mfspr r23,SPRN_SPRG3 /* If from user, fix up THREAD.regs */ + beq 2f /* No, it is from the kernel; branch. */ + mfspr r24,SPRN_DBCR0 + stw r24,THREAD_DBCR0(r23) /* Save Debug Control in thread_struct */ + addi r24,r1,STACK_FRAME_OVERHEAD + stw r24,PT_REGS(r23) +2: addi r2,r23,-THREAD /* Set r2 to current thread */ + mflr r23 + lwz r24,8(r23) /* Emulate classic PPC vectors */ + stw r24,TRAP(r21) + li r22,RESULT + /* No need to put an erratum #77 workaround here + because interrupts are currently disabled */ + stwcx. r22,r22,r21 /* Clear the reservation */ + li r22,0 + stw r22,RESULT(r21) + mtspr SPRN_SPRG2,r22 /* r1 is now the kernel stack pointer */ + addi r24,r2,TASK_STRUCT_SIZE /* Check for kernel stack overflow */ + cmplw cr0,r1,r2 + cmplw cr1,r1,r24 + crand cr1,cr1,cr4 + bgt- stack_ovf /* If r2 < r1 < r2 + TASK_STRUCT_SIZE */ + lwz r24,0(r23) /* Virtual address of the handler */ + lwz r23,4(r23) /* Handler return pointer */ + cmpwi cr0,r7,STND_EXC /* What type of exception is this? */ + bne 3f /* It is a critical/machine check exception... */ + + /* Standard exception jump path + */ + + /* We have to recover r7 from the register save stack. + * It was used to indicate standard/critical exception. In + * the case of a standard exception that is the system call + * trap, it may have originally contained one of the syscall + * parameters and we have to get it back now. + */ + lwz r7,GPR7(r21) + mtspr SPRN_SRR0,r24 /* Set up the instruction pointer */ + mtspr SPRN_SRR1,r20 /* Set up the machine state register */ + mtlr r23 /* Set up the return pointer */ + SYNC + rfi + + /* Critical/Machine check exception jump path + */ +3: cmpwi r7,CRIT_EXC /* Critical or machine check ? */ + mtlr r23 /* Set up the return pointer */ + bne 4f + mtspr SPRN_CSRR0,r24 /* Set up the instruction pointer */ + mtspr SPRN_CSRR1,r20 /* Set up the machine state register */ + SYNC + rfci + +4: mtspr SPRN_MCSRR0,r24 /* Set up the instruction pointer */ + mtspr SPRN_MCSRR1,r20 /* Set up the machine state register */ + SYNC + RFMCI + +/* On kernel stack overlow, load up an initial stack pointer and call + * StackOverflow(regs), which should NOT return. + */ + +stack_ovf: + addi r3,r1,STACK_FRAME_OVERHEAD + lis r1,init_task_union@ha + addi r1,r1,init_task_union@l + addi r1,r1,TASK_UNION_SIZE - STACK_FRAME_OVERHEAD + lis r24,StackOverflow@ha + addi r24,r24,StackOverflow@l + li r20,MSR_KERNEL + mtspr SPRN_SRR0,r24 + mtspr SPRN_SRR1,r20 + SYNC + rfi + +/* + * We put a few things here that have to be page-aligned. This stuff + * goes at the beginning of the data segment, which is page-aligned. + */ + .data +_GLOBAL(sdata) +_GLOBAL(empty_zero_page) + .space 4096 + +/* + * To support >32-bit physical addresses, we use an 8KB pgdir. + */ +_GLOBAL(swapper_pg_dir) + .space 8192 + +/* + * This space gets a copy of optional info passed to us by the bootstrap + * which is used to pass parameters into the kernel like root=/dev/sda1, etc. + */ +_GLOBAL(cmd_line) + .space 512 + +/* + * Room for two PTE pointers, usually the kernel and current user pointers + * to their respective root page table. + */ +abatron_pteptrs: + .space 8 diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/ibm440gp_common.c cset-v2.4.20/arch/ppc/kernel/ibm440gp_common.c --- cset-v2.4.20~/arch/ppc/kernel/ibm440gp_common.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/ibm440gp_common.c 2004-11-02 17:38:17.000000000 +0900 @@ -0,0 +1,78 @@ +/* + * arch/ppc/syslib/ibm440gp_common.c + * + * PPC440GP system library + * + * Matt Porter + * Copyright 2002-2003 MontaVista Software Inc. + * + * Eugene Surovegin or + * Copyright (c) 2003 Zultys Technologies + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include +#include +#include +#include +#include +#include + +/* + * Calculate 440GP clocks + */ +void __init ibm440gp_get_clocks(struct ibm44x_clocks* p, unsigned int sys_clk, + unsigned int ser_clk) +{ + u32 cpc0_sys0 = mfdcr(DCRN_CPC0_SYS0); + u32 cpc0_cr0 = mfdcr(DCRN_CPC0_CR0); + u32 opdv, epdv; + + if (cpc0_sys0 & 0x2){ + /* Bypass system PLL */ + p->cpu = p->plb = sys_clk; + } + else { + u32 fbdv, fwdva, fwdvb, m, vco; + + fbdv = (cpc0_sys0 >> 18) & 0x0f; + if (!fbdv) + fbdv = 16; + + fwdva = 8 - ((cpc0_sys0 >> 15) & 0x7); + fwdvb = 8 - ((cpc0_sys0 >> 12) & 0x7); + + /* Feedback path */ + if (cpc0_sys0 & 0x00000080){ + /* PerClk */ + m = fwdvb * opdv * epdv; + } + else { + /* CPU clock */ + m = fbdv * fwdva; + } + vco = sys_clk * m; + p->cpu = vco / fwdva; + p->plb = vco / fwdvb; + } + + opdv = ((cpc0_sys0 >> 10) & 0x3) + 1; + epdv = ((cpc0_sys0 >> 8) & 0x3) + 1; + + p->opb = p->plb / opdv; + p->ebc = p->opb / epdv; + + if (cpc0_cr0 & 0x00400000){ + /* External UART clock */ + p->uart0 = p->uart1 = ser_clk; + } + else { + /* Internal UART clock */ + u32 uart_div = ((cpc0_cr0 >> 16) & 0x1f) + 1; + p->uart0 = p->uart1 = p->plb / uart_div; + } +} diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/ibm440gp_common.h cset-v2.4.20/arch/ppc/kernel/ibm440gp_common.h --- cset-v2.4.20~/arch/ppc/kernel/ibm440gp_common.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/ibm440gp_common.h 2004-11-02 17:38:17.000000000 +0900 @@ -0,0 +1,35 @@ +/* + * arch/ppc/kernel/ibm440gp_common.h + * + * PPC440GP system library + * + * Eugene Surovegin or + * Copyright (c) 2003 Zultys Technologies + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#ifdef __KERNEL__ +#ifndef __PPC_SYSLIB_IBM440GP_COMMON_H +#define __PPC_SYSLIB_IBM440GP_COMMON_H + +#ifndef __ASSEMBLY__ + +#include +#include +#include + +/* + * Please, refer to the Figure 13.1 in 440GP user manual + * + * if internal UART clock is used, ser_clk is ignored + */ +void ibm440gp_get_clocks(struct ibm44x_clocks*, unsigned int sys_clk, + unsigned int ser_clk) __init; + +#endif /* __ASSEMBLY__ */ +#endif /* __PPC_SYSLIB_IBM440GP_COMMON_H */ +#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/ibm440gx_common.c cset-v2.4.20/arch/ppc/kernel/ibm440gx_common.c --- cset-v2.4.20~/arch/ppc/kernel/ibm440gx_common.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/ibm440gx_common.c 2004-11-02 17:54:22.000000000 +0900 @@ -0,0 +1,192 @@ +/* + * arch/ppc/kernel/ibm440gx_common.c + * + * PPC440GX system library + * + * Eugene Surovegin or + * Copyright (c) 2003 Zultys Technologies + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include +#include +#include +#include +#include +#include +#include + +/* + * Calculate 440GX clocks + */ +static inline u32 __fix_zero(u32 v, u32 def){ + return v ? v : def; +} + +void __init ibm440gx_get_clocks(struct ibm44x_clocks* p, unsigned int sys_clk, + unsigned int ser_clk) +{ + u32 pllc = CPR_READ(DCRN_CPR_PLLC); + u32 plld = CPR_READ(DCRN_CPR_PLLD); + u32 uart0 = SDR_READ(DCRN_SDR_UART0); + u32 uart1 = SDR_READ(DCRN_SDR_UART1); + + /* Dividers */ + u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32); + u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16); + u32 fwdvb = __fix_zero((plld >> 8) & 7, 8); + u32 lfbdv = __fix_zero(plld & 0x3f, 64); + u32 pradv0 = __fix_zero((CPR_READ(DCRN_CPR_PRIMAD) >> 24) & 7, 8); + u32 prbdv0 = __fix_zero((CPR_READ(DCRN_CPR_PRIMBD) >> 24) & 7, 8); + u32 opbdv0 = __fix_zero((CPR_READ(DCRN_CPR_OPBD) >> 24) & 3, 4); + u32 perdv0 = __fix_zero((CPR_READ(DCRN_CPR_PERD) >> 24) & 3, 4); + + /* Input clocks for primary dividers */ + u32 clk_a, clk_b; + + if (pllc & 0x40000000){ + u32 m; + + /* Feedback path */ + switch ((pllc >> 24) & 7){ + case 0: + /* PLLOUTx */ + m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv; + break; + case 1: + /* CPU */ + m = fwdva * pradv0; + break; + case 5: + /* PERClk */ + m = fwdvb * prbdv0 * opbdv0 * perdv0; + break; + default: + printk(KERN_EMERG "invalid PLL feedback source\n"); + goto bypass; + } + m *= fbdv; + p->vco = sys_clk * m; + clk_a = p->vco / fwdva; + clk_b = p->vco / fwdvb; + } + else { +bypass: + /* Bypass system PLL */ + p->vco = 0; + clk_a = clk_b = sys_clk; + } + + p->cpu = clk_a / pradv0; + p->plb = clk_b / prbdv0; + p->opb = p->plb / opbdv0; + p->ebc = p->opb / perdv0; + + /* UARTs clock */ + if (uart0 & 0x00800000) + p->uart0 = ser_clk; + else + p->uart0 = p->plb / __fix_zero(uart0 & 0xff, 256); + + if (uart1 & 0x00800000) + p->uart1 = ser_clk; + else + p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256); +} + +/* Enable L2 cache (call with IRQs disabled) */ +void __init ibm440gx_l2c_enable(void){ + u32 r; + + asm volatile ("sync" ::: "memory"); + + /* Disable SRAM */ + mtdcr(DCRN_SRAM0_DPC, mfdcr(DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE); + mtdcr(DCRN_SRAM0_SB0CR, mfdcr(DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK); + mtdcr(DCRN_SRAM0_SB1CR, mfdcr(DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK); + mtdcr(DCRN_SRAM0_SB2CR, mfdcr(DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK); + mtdcr(DCRN_SRAM0_SB3CR, mfdcr(DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK); + + /* Enable L2_MODE without ICU/DCU */ + r = mfdcr(DCRN_L2C0_CFG) & ~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK); + r |= L2C_CFG_L2M | L2C_CFG_SS_256; + mtdcr(DCRN_L2C0_CFG, r); + + mtdcr(DCRN_L2C0_ADDR, 0); + + /* Hardware Clear Command */ + mtdcr(DCRN_L2C0_CMD, L2C_CMD_HCC); + while (!(mfdcr(DCRN_L2C0_SR) & L2C_SR_CC)) ; + + /* Clear Cache Parity and Tag Errors */ + mtdcr(DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE); + + /* Enable 64G snoop region starting at 0 */ + r = mfdcr(DCRN_L2C0_SNP0) & ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK); + r |= L2C_SNP_SSR_32G | L2C_SNP_ESR; + mtdcr(DCRN_L2C0_SNP0, r); + + r = mfdcr(DCRN_L2C0_SNP1) & ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK); + r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR; + mtdcr(DCRN_L2C0_SNP1, r); + + asm volatile ("sync" ::: "memory"); + + /* Enable ICU/DCU ports */ + r = mfdcr(DCRN_L2C0_CFG); + r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM + | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM | L2C_CFG_TPEI | L2C_CFG_CPEI + | L2C_CFG_NAM | L2C_CFG_NBRM); + r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN + | L2C_CFG_SMCM; + mtdcr(DCRN_L2C0_CFG, r); + + asm volatile ("sync; isync" ::: "memory"); +} + +/* Disable L2 cache (call with IRQs disabled) */ +void __init ibm440gx_l2c_disable(void){ + u32 r; + + asm volatile ("sync" ::: "memory"); + + /* Disable L2C mode */ + r = mfdcr(DCRN_L2C0_CFG) & ~(L2C_CFG_L2M | L2C_CFG_ICU | L2C_CFG_DCU); + mtdcr(DCRN_L2C0_CFG, r); + + /* Enable SRAM */ + mtdcr(DCRN_SRAM0_DPC, mfdcr(DCRN_SRAM0_DPC) | SRAM_DPC_ENABLE); + mtdcr(DCRN_SRAM0_SB0CR, + SRAM_SBCR_BAS0 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW); + mtdcr(DCRN_SRAM0_SB1CR, + SRAM_SBCR_BAS1 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW); + mtdcr(DCRN_SRAM0_SB2CR, + SRAM_SBCR_BAS2 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW); + mtdcr(DCRN_SRAM0_SB3CR, + SRAM_SBCR_BAS3 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW); + + asm volatile ("sync; isync" ::: "memory"); +} + +int ibm440gx_show_cpuinfo(struct seq_file *m){ + + u32 l2c_cfg = mfdcr(DCRN_L2C0_CFG); + const char* s; + if (l2c_cfg & L2C_CFG_L2M){ + switch (l2c_cfg & (L2C_CFG_ICU | L2C_CFG_DCU)){ + case L2C_CFG_ICU: s = "I-Cache only"; break; + case L2C_CFG_DCU: s = "D-Cache only"; break; + default: s = "I-Cache/D-Cache"; break; + } + } + else + s = "disabled"; + + seq_printf(m, "L2-Cache\t: %s (0x%08x 0x%08x)\n", s, + l2c_cfg, mfdcr(DCRN_L2C0_SR)); +} + diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/ibm440gx_common.h cset-v2.4.20/arch/ppc/kernel/ibm440gx_common.h --- cset-v2.4.20~/arch/ppc/kernel/ibm440gx_common.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/ibm440gx_common.h 2004-11-02 17:52:41.000000000 +0900 @@ -0,0 +1,42 @@ +/* + * arch/ppc/kernel/ibm440gx_common.h + * + * PPC440GX system library + * + * Eugene Surovegin or + * Copyright (c) 2003 Zultys Technologies + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#ifdef __KERNEL__ +#ifndef __PPC_SYSLIB_IBM440GX_COMMON_H +#define __PPC_SYSLIB_IBM440GX_COMMON_H + +#ifndef __ASSEMBLY__ + +#include +#include +#include +#include + +/* + * Please, refer to the Figure 14.1 in 440GX user manual + * + * if internal UART clock is used, ser_clk is ignored + */ +void ibm440gx_get_clocks(struct ibm44x_clocks*, unsigned int sys_clk, + unsigned int ser_clk) __init; + +/* Enable L2 cache */ +void ibm440gx_l2c_enable(void) __init; + +/* Add L2C info to /proc/cpuinfo */ +int ibm440gx_show_cpuinfo(struct seq_file*); + +#endif /* __ASSEMBLY__ */ +#endif /* __PPC_SYSLIB_IBM440GX_COMMON_H */ +#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/ibm44x_common.c cset-v2.4.20/arch/ppc/kernel/ibm44x_common.c --- cset-v2.4.20~/arch/ppc/kernel/ibm44x_common.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/ibm44x_common.c 2004-11-01 22:35:09.000000000 +0900 @@ -0,0 +1,37 @@ +/* + * arch/ppc/kernel/ibm44x_common.c + * + * PPC44x system library + * + * Matt Porter + * Copyright 2002-2003 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include +#include +#include +#include + +phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size) +{ + phys_addr_t page_4gb = 0; + + /* + * Trap the least significant 32-bit portions of an + * address in the 440's 36-bit address space. Fix + * them up with the appropriate ERPN + */ + if ((addr >= PPC44x_IO_LO) && (addr < PPC44x_IO_HI)) + page_4gb = PPC44x_IO_PAGE; + else if ((addr >= PPC44x_PCICFG_LO) && (addr < PPC44x_PCICFG_HI)) + page_4gb = PPC44x_PCICFG_PAGE; + else if ((addr >= PPC44x_PCIMEM_LO) && (addr < PPC44x_PCIMEM_HI)) + page_4gb = PPC44x_PCIMEM_PAGE; + + return (page_4gb | addr); +}; diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/ibm44x_common.h cset-v2.4.20/arch/ppc/kernel/ibm44x_common.h --- cset-v2.4.20~/arch/ppc/kernel/ibm44x_common.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/ibm44x_common.h 2004-11-02 17:38:17.000000000 +0900 @@ -0,0 +1,36 @@ +/* + * arch/ppc/kernel/ibm44x_common.h + * + * PPC44x system library + * + * Eugene Surovegin or + * Copyright (c) 2003 Zultys Technologies + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#ifdef __KERNEL__ +#ifndef __PPC_SYSLIB_IBM44x_COMMON_H +#define __PPC_SYSLIB_IBM44x_COMMON_H + +#ifndef __ASSEMBLY__ + +/* + * All clocks are in Hz + */ +struct ibm44x_clocks { + unsigned int vco; /* VCO, 0 if system PLL is bypassed */ + unsigned int cpu; /* CPUCoreClk */ + unsigned int plb; /* PLBClk */ + unsigned int opb; /* OPBClk */ + unsigned int ebc; /* PerClk */ + unsigned int uart0; + unsigned int uart1; +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __PPC_SYSLIB_IBM44x_COMMON_H */ +#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/misc.S cset-v2.4.20/arch/ppc/kernel/misc.S --- cset-v2.4.20~/arch/ppc/kernel/misc.S 2004-10-25 15:02:57.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/misc.S 2004-11-01 22:35:09.000000000 +0900 @@ -351,6 +351,33 @@ * Flush MMU TLB */ _GLOBAL(_tlbia) +#if defined(CONFIG_40x) && defined(CONFIG_PIN_TLB) + /* This needs to be coordinated with other pinning functions since + * we don't keep a memory location of number of entries to reduce + * cache pollution during these operations. + */ + lis r3, 0 + sync +1: + tlbwe r3, r3, TLB_TAG /* just ensure V is clear */ + addi r3, r3, 1 /* so r3 works fine for that */ + cmpwi 0, r3, 61 /* reserve last two entries */ + ble 1b + isync +#elif defined(CONFIG_44x) + lis r3,0 + sync +1: + tlbwe r3,r3,PPC44x_TLB_PAGEID + addi r3,r3,1 + /* Load high watermark */ + lis r4,tlb_44x_hwater@h + ori r4,r4,tlb_44x_hwater@l + lwz r5,0(r4) + cmpw 0,r3,r5 + ble 1b + isync +#else /* !(CONFIG_40x || CONFIG_44x) */ #if defined(CONFIG_SMP) mfmsr r10 SYNC @@ -377,12 +404,48 @@ mtmsr r10 SYNC #endif /* CONFIG_SMP */ +#endif /* defined(CONFIG_40x) && defined(CONFIG_PIN_TLB) */ blr /* * Flush MMU TLB for a particular address */ _GLOBAL(_tlbie) +#ifdef CONFIG_40x + tlbsx. r3, 0, r3 + bne 10f + sync + /* There are only 64 TLB entries, so r3 < 64, which means bit 25, is clear. + * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate + * the TLB entry. */ + tlbwe r3, r3, TLB_TAG + isync +10: +#elif defined(CONFIG_44x) + mfspr r4,SPRN_MMUCR /* Get MMUCR */ + lis r5,PPC44x_MMUCR_STS@h + ori r5,r5,PPC44x_MMUCR_TID@l /* Create mask */ + andc r4,r4,r5 /* Clear out TID/STS bits */ + mfspr r5,SPRN_PID /* Get PID */ + or r4,r4,r5 /* Set TID bits */ + mfmsr r6 /* Get MSR */ + andi. r6,r6,MSR_IS@l /* TS=1? */ + beq 11f /* If not, leave STS=0 */ + oris r4,r4,PPC44x_MMUCR_STS@h /* Set STS=1 */ +11: mtspr SPRN_MMUCR, r4 /* Put MMUCR */ + + tlbsx. r3, 0, r3 + bne 10f + sync + /* There are only 64 TLB entries, so r3 < 64, + * which means bit 22, is clear. Since 22 is + * the V bit in the TLB_PAGEID, loading this + * value will invalidate the TLB entry. + */ + tlbwe r3, r3, PPC44x_TLB_PAGEID + isync +10: +#else /* !(CONFIG_40x || CONFIG_44x) */ #if defined(CONFIG_SMP) mfmsr r10 SYNC @@ -396,6 +459,7 @@ 10: lwarx r7,0,r9 cmpi 0,r7,0 bne- 10b + PPC405_ERR77(0,r9) stwcx. r8,0,r9 bne- 10b #endif /* CONFIG_SMP */ @@ -409,6 +473,7 @@ mtmsr r10 SYNC #endif +#endif /* CONFIG_40x */ blr /* @@ -420,9 +485,18 @@ isync lis r5, IDC_INVALL@h mtspr IC_CST, r5 -#elif defined(CONFIG_4xx) +#elif CONFIG_4xx +#ifdef CONFIG_403GCX + li r3, 512 + mtctr r3 + lis r4, KERNELBASE@h +1: iccci 0, r4 + addi r4, r4, 16 + bdnz 1b +#else lis r3, KERNELBASE@h iccci 0,r3 +#endif #else mfspr r3,PVR rlwinm r3,r3,16,16,31 @@ -432,7 +506,7 @@ mfspr r3,HID0 ori r3,r3,HID0_ICFI mtspr HID0,r3 -#endif /* CONFIG_8xx */ +#endif /* CONFIG_8xx/4xx */ isync blr @@ -532,6 +606,27 @@ sync /* wait for dcbi's to get to ram */ blr +#ifdef CONFIG_NOT_COHERENT_CACHE +/* + * 40x cores have 8K or 16K dcache and 32 byte line size. + * 44x has a 32K dcache and 32 byte line size. + * 8xx has 1, 2, 4, 8K variants. + * For now, cover the worst case of the 440. + * Must be called with external interrupts disabled. + */ +#define CACHE_NWAYS 64 +#define CACHE_NLINES 16 + +_GLOBAL(flush_dcache_all) + li r4, (2 * CACHE_NWAYS * CACHE_NLINES) + mtctr r4 + lis r5, KERNELBASE@h +1: lwz r3, 0(r5) /* Load one word from every line */ + addi r5, r5, L1_CACHE_LINE_SIZE + bdnz 1b + blr +#endif /* CONFIG_NOT_COHERENT_CACHE */ + /* * Flush a particular page from the data cache to RAM. * Note: this is necessary because the instruction cache does *not* @@ -866,7 +961,7 @@ * and exceptions as if the cpu had performed the load or store. */ -#if defined(CONFIG_4xx) +#ifdef CONFIG_4xx _GLOBAL(cvt_fd) lfs 0,0(r3) stfd 0,0(r4) diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/mk_defs.c cset-v2.4.20/arch/ppc/kernel/mk_defs.c --- cset-v2.4.20~/arch/ppc/kernel/mk_defs.c 2004-10-25 15:05:03.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/mk_defs.c 2004-11-01 22:35:09.000000000 +0900 @@ -59,6 +59,9 @@ DEFINE(THREAD_VRSAVE, offsetof(struct thread_struct, vrsave)); DEFINE(THREAD_VSCR, offsetof(struct thread_struct, vscr)); #endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_4xx + DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0)); +#endif /* Interrupt register frame */ DEFINE(TASK_UNION_SIZE, sizeof(union task_union)); DEFINE(STACK_FRAME_OVERHEAD, STACK_FRAME_OVERHEAD); diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/ocp.c cset-v2.4.20/arch/ppc/kernel/ocp.c --- cset-v2.4.20~/arch/ppc/kernel/ocp.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/ocp.c 2004-11-01 22:35:09.000000000 +0900 @@ -0,0 +1,450 @@ +/* + * ocp.c + * + * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org) + * Mipsys - France + * + " Derived from work (c) Armin Kuster akuster@pacbell.net + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +//#define DBG(x) printk x +#define DBG(x) + +extern struct ocp_def core_ocp[]; /* Static list of devices, provided by + CPU core */ + +LIST_HEAD(ocp_devices); /* List of all OCP devices */ +LIST_HEAD(ocp_drivers); /* List of all OCP drivers */ +DECLARE_RWSEM(ocp_devices_sem); /* Global semaphores for those lists */ +DECLARE_MUTEX(ocp_drivers_sem); /* Global semaphores for those lists */ + +static int ocp_inited; + +/** + * ocp_driver_match - Match one driver to one device + * @drv: driver to match + * @dev: device to match + * + * This function returns 0 if the driver and device don't match + */ +static int +ocp_driver_match(struct ocp_driver *drv, struct ocp_device *dev) +{ + const struct ocp_device_id *ids = drv->id_table; + + if (!ids) + return 0; + + while (ids->vendor || ids->function) { + if ((ids->vendor == OCP_ANY_ID + || ids->vendor == dev->def->vendor) + && (ids->function == OCP_ANY_ID + || ids->function == dev->def->function)) + return 1; + ids++; + } + return 0; +} + + +/** + * ocp_bind_drivers - Match all drivers with all devices + * @candidate: driver beeing registered + * + * This function is called on driver registration and device discovery, + * it redo the matching of all "driverless" devices with all possible + * driver candidates. + * The driver beeing registered can be optionally passed in, in which + * case, the function will return -ENODEV is no match have been found + * or if all matches failed with a different code than -EAGAIN + */ +static int +ocp_bind_drivers(struct ocp_driver *candidate) +{ + struct list_head *deventry, *drventry; + struct ocp_device *dev; + struct ocp_driver *drv; + int one_again, one_match; + int count = 0; + + DBG(("ocp: binding drivers...\n")); + do { + /* We re-do the match loop if we had a sucess match and got one -EAGAIN + */ + one_match = one_again = 0; + down_read(&ocp_devices_sem); + list_for_each(deventry, &ocp_devices) { + dev = list_entry(deventry, struct ocp_device, link); + if (dev->driver != NULL) + continue; + DBG(("ocp: device %s unmatched, trying to match...\n", dev->name)); + list_for_each(drventry, &ocp_drivers) { + drv = list_entry(drventry, struct ocp_driver, link); + if (ocp_driver_match(drv, dev)) { + int rc; + + /* Hrm... shall we set dev->driver after or before ? */ + DBG(("ocp: match with driver %s, calling probe...\n", drv->name)); + rc = drv->probe(dev); + DBG(("ocp: probe result: %d\n", rc)); + if (rc == 0) { + /* Driver matched, next device */ + dev->driver = drv; + one_match = 1; + if (drv == candidate) + count++; + break; + } else if (rc == -EAGAIN) { + /* Driver matched but asked for later call, next device */ + one_again = 1; + if (drv == candidate) + count++; + break; + } + } + } + } + up_read(&ocp_devices_sem); + } while(one_match && one_again); + DBG(("ocp: binding drivers... done.\n")); + + return count; +} + +/** + * ocp_register_driver - Register an OCP driver + * @drv: pointer to statically defined ocp_driver structure + * + * The driver's probe() callback is called either recursively + * by this function or upon later call of ocp_init + * + * NOTE: Probe is called with ocp_drivers_sem heocp_find_deviceld, it shouldn't + * call ocp_register/unregister_driver on his own code path. + * however, it _can_ call ocp_find_device(). + * + * NOTE2: Detection of devices is a 2 pass step on this implementation, + * hotswap isn't supported. First, all OCP devices are put in the device + * list, _then_ all drivers are probed on each match. + * + * NOTE3: Drivers are allowed to return -EAGAIN from the probe() routine. + * this will cause them to be called again for this specific device as + * soon as another device have been probed or another driver registered. + * this, gives a simple way for a driver like EMAC to wait for another driver, + * like MAL to be up. There is potentially a small race if MAL happens to + * unregister, but this is hopefully never happening. + * + * This function returns a count of how many devices actually matched + * (wether the probe routine returned 0 or -EAGAIN, a different error + * code isn't considered as a match). + */ + +int +ocp_register_driver(struct ocp_driver *drv) +{ + int rc = 0; + + DBG(("ocp: ocp_register_driver(%s)...\n", drv->name)); + + /* Add to driver list */ + down(&ocp_drivers_sem); + list_add_tail(&drv->link, &ocp_drivers); + + /* Check matching devices */ + rc = ocp_bind_drivers(drv); + + up(&ocp_drivers_sem); + + DBG(("ocp: ocp_register_driver(%s)... done, count: %d.\n", drv->name, rc)); + + return rc; +} + +/** + * ocp_unregister_driver - Unregister an OCP driver + * @drv: pointer to statically defined ocp_driver structure + * + * The driver's remove() callback is called recursively + * by this function for any device already registered + */ + +void +ocp_unregister_driver(struct ocp_driver *drv) +{ + struct ocp_device *dev; + struct list_head *entry; + + DBG(("ocp: ocp_unregister_driver(%s)...\n", drv->name)); + + /* Call remove() routine for all devices using it */ + down(&ocp_drivers_sem); + down_read(&ocp_devices_sem); + list_for_each(entry, &ocp_devices) { + dev = list_entry(entry, struct ocp_device, link); + if (dev->driver == drv) { + drv->remove(dev); + dev->driver = NULL; + dev->drvdata = NULL; + } + } + up_read(&ocp_devices_sem); + + /* Unlink driver structure */ + list_del_init(&drv->link); + up(&ocp_drivers_sem); + + DBG(("ocp: ocp_unregister_driver(%s)... done.\n", drv->name)); +} + +/** + * ocp_find_device - Find a device by function & index + * @vendor: vendor ID of the device (or OCP_ANY_ID) + * @function: function code of the device (or OCP_ANY_ID) + * @idx: index of the device (or OCP_ANY_INDEX) + * + * This function allows a lookup of a given function by it's + * index, it's typically used to find the MAL or ZMII associated + * with an EMAC or similar horrors. + * You can pass vendor, though you usually want OCP_ANY_ID there... + */ +struct ocp_device * +ocp_find_device(unsigned int vendor, unsigned int function, int index) +{ + struct list_head *entry; + struct ocp_device *dev, *found = NULL; + + DBG(("ocp: ocp_find_device(vendor: %x, function: %x, index: %d)...\n", + vendor, function, index)); + + down_read(&ocp_devices_sem); + list_for_each(entry, &ocp_devices) { + dev = list_entry(entry, struct ocp_device, link); + if (vendor != OCP_ANY_ID && vendor != dev->def->vendor) + continue; + if (function != OCP_ANY_ID && function != dev->def->function) + continue; + if (index != OCP_ANY_INDEX && index != dev->def->index) + continue; + found = dev; + break; + } + up_read(&ocp_devices_sem); + + DBG(("ocp: ocp_find_device(vendor: %x, function: %x, index: %d)... done.\n", + vendor, function, index)); + + return found; +} + +/** + * ocp_add_one_device - Add a device + * @def: static device definition structure + * + * This function is solely meant to be called by ocp_init + * to add one device from the core static list to the + * device list + */ +static void +ocp_add_one_device(struct ocp_def *def) +{ + struct ocp_device *dev; + + dev = kmalloc(sizeof(*dev), GFP_KERNEL); + if (dev == NULL) + return; + memset(dev, 0, sizeof(*dev)); + dev->def = def; + dev->current_state = 4; + sprintf(dev->name, "OCP device %04x:%04x:%04x", + dev->def->vendor, dev->def->function, dev->def->index); + list_add_tail(&dev->link, &ocp_devices); +} + +#ifdef CONFIG_PM +/* + * OCP Power management.. + * + * This needs to be done centralized, so that we power manage PCI + * devices in the right order: we should not shut down PCI bridges + * before we've shut down the devices behind them, and we should + * not wake up devices before we've woken up the bridge to the + * device.. Eh? + * + * We do not touch devices that don't have a driver that exports + * a suspend/resume function. That is just too dangerous. If the default + * PCI suspend/resume functions work for a device, the driver can + * easily implement them (ie just have a suspend function that calls + * the pci_set_power_state() function). + * + * BenH: Implementation here couldn't work properly. This version + * slightly modified and _might_ be more useable, but real + * PM support will probably have to wait for 2.5 + */ + +static int ocp_pm_save_state_device(struct ocp_device *dev, u32 state) +{ + int error = 0; + if (dev) { + struct ocp_driver *driver = dev->driver; + if (driver && driver->save_state) + error = driver->save_state(dev,state); + } + return error; +} + +static int ocp_pm_suspend_device(struct ocp_device *dev, u32 state) +{ + int error = 0; + if (dev) { + struct ocp_driver *driver = dev->driver; + if (driver && driver->suspend) + error = driver->suspend(dev,state); + } + return error; +} + +static int ocp_pm_resume_device(struct ocp_device *dev) +{ + int error = 0; + if (dev) { + struct ocp_driver *driver = dev->driver; + if (driver && driver->resume) + error = driver->resume(dev); + } + return error; +} + +static int +ocp_pm_callback(struct pm_dev *pm_device, pm_request_t rqst, void *data) +{ + int error = 0; + struct list_head *entry; + struct ocp_device *dev; + + down(&ocp_drivers_sem); + down_read(&ocp_devices_sem); + + list_for_each(entry, &ocp_devices) { + dev = list_entry(entry, struct ocp_device, link); + switch (rqst) { + case PM_SAVE_STATE: + error = ocp_pm_save_state_device(dev, 3); + break; + case PM_SUSPEND: + error = ocp_pm_suspend_device(dev, 3); + break; + case PM_RESUME: + error = ocp_pm_resume_device(dev); + break; + default: break; + } + if (error) + break; + } + return error; +} + +/* + * Is this ever used ? + */ +void +ppc4xx_cpm_fr(u32 bits, int val) +{ + unsigned long flags; + + save_flags(flags); + cli(); + + if (val) + mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | bits); + else + mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~bits); + + restore_flags(flags); +} +#endif /* CONFIG_PM */ + +/** + * ocp_init - Init OCP device management + * + * This function is meant to be called once, and only once to initialize + * the OCP device management and build the list of devices. Note that + * it can actually be called at any time, it's perfectly legal to + * register drivers before ocp_init() is called + */ +int +ocp_init(void) +{ + struct ocp_def *def; + + /* ocp_init is by default an initcall. If your arch requires this to + * be called earlier, then go on, ocp_init is non-static for that purpose, + * and can safely be called twice + */ + if (ocp_inited) + return 0; + ocp_inited = 1; + + DBG(("ocp: ocp_init()...\n")); + + /* Fill the devices list */ + down_write(&ocp_devices_sem); + for (def = core_ocp; def->vendor != OCP_VENDOR_INVALID; def++) + ocp_add_one_device(def); + up_write(&ocp_devices_sem); + + DBG(("ocp: ocp_init()... added...\n")); + + /* Call drivers probes */ + down(&ocp_drivers_sem); + ocp_bind_drivers(NULL); + up(&ocp_drivers_sem); + +#ifdef CONFIG_PM + pm_register(PM_SYS_DEV, 0, ocp_pm_callback); +#endif + + DBG(("ocp: ocp_init()... done.\n")); + + return 0; +} + +__initcall(ocp_init); + +EXPORT_SYMBOL(ocp_register_driver); +EXPORT_SYMBOL(ocp_unregister_driver); diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/pci-dma.c cset-v2.4.20/arch/ppc/kernel/pci-dma.c --- cset-v2.4.20~/arch/ppc/kernel/pci-dma.c 2004-10-25 15:00:46.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/pci-dma.c 2004-11-01 22:35:09.000000000 +0900 @@ -23,13 +23,20 @@ void *ret; int gfp = GFP_ATOMIC; - if (hwdev == NULL || hwdev->dma_mask != 0xffffffff) + if (hwdev == NULL || hwdev->dma_mask < 0xffffffff) gfp |= GFP_DMA; + +#ifdef CONFIG_NOT_COHERENT_CACHE + ret = consistent_alloc(gfp, size, dma_handle); +#else ret = (void *)__get_free_pages(gfp, get_order(size)); +#endif if (ret != NULL) { memset(ret, 0, size); +#ifndef CONFIG_NOT_COHERENT_CACHE *dma_handle = virt_to_bus(ret); +#endif } return ret; } @@ -37,5 +44,9 @@ void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle) { +#ifdef CONFIG_NOT_COHERENT_CACHE + consistent_free(vaddr); +#else free_pages((unsigned long)vaddr, get_order(size)); +#endif } diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/ppc4xx_pic.c cset-v2.4.20/arch/ppc/kernel/ppc4xx_pic.c --- cset-v2.4.20~/arch/ppc/kernel/ppc4xx_pic.c 2004-10-25 14:58:21.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/ppc4xx_pic.c 2004-11-01 22:35:09.000000000 +0900 @@ -18,10 +18,14 @@ * there are eight internal interrupts for the on-chip serial port * (SPU), DMA controller, and JTAG controller. * - * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32 - * possible interrupts as well. There are seven, configurable external - * interrupt pins and there are 17 internal interrupts for the on-chip - * serial port, DMA controller, on-chip Ethernet controller, PCI, etc. + * The PowerPC 405/440 cores' Universal Interrupt Controller (UIC) has + * 32 possible interrupts as well. Depending on the core and SoC + * implementation, a portion of the interrrupts are used for on-chip + * peripherals and a portion of the interrupts are available to be + * configured for external devices generating interrupts. + * + * The PowerNP and 440GP (and most likely future implementations) have + * cascaded UICs. * */ @@ -36,9 +40,25 @@ #include /* Global Variables */ - struct hw_interrupt_type *ppc4xx_pic; +/* + * We define 4xxIRQ_InitSenses table thusly: + * bit 0x1: sense, 0 for edge and 1 for level. + * bit 0x2: polarity, 0 for negative, 1 for positive. + */ +unsigned int ibm4xxPIC_NumInitSenses __initdata = 0; +unsigned char *ibm4xxPIC_InitSenses __initdata = NULL; +/* Six of one, half dozen of the other....#ifdefs, separate files, + * other tricks..... + * + * There are basically two types of interrupt controllers, the 403 AIC + * and the "others" with UIC. I just kept them both here separated + * with #ifdefs, but it seems to change depending upon how supporting + * files (like ppc4xx.h) change. -- Dan. + */ + +#ifdef CONFIG_403 /* Function Prototypes */ @@ -46,10 +66,6 @@ static void ppc403_aic_disable(unsigned int irq); static void ppc403_aic_disable_and_ack(unsigned int irq); -static void ppc405_uic_enable(unsigned int irq); -static void ppc405_uic_disable(unsigned int irq); -static void ppc405_uic_disable_and_ack(unsigned int irq); - static struct hw_interrupt_type ppc403_aic = { "403GC AIC", NULL, @@ -60,55 +76,11 @@ 0 }; -static struct hw_interrupt_type ppc405_uic = { - "405GP UIC", - NULL, - NULL, - ppc405_uic_enable, - ppc405_uic_disable, - ppc405_uic_disable_and_ack, - 0 -}; - -/* - * Document me. - */ -void __init -ppc4xx_pic_init(void) -{ - unsigned long ver = PVR_VER(mfspr(SPRN_PVR)); - - switch (ver) { - - case PVR_VER(PVR_403GC): - /* - * Disable all external interrupts until they are - * explicity requested. - */ - ppc_cached_irq_mask[0] = 0; - mtdcr(DCRN_EXIER, 0); - - ppc4xx_pic = &ppc403_aic; - break; - - case PVR_VER(PVR_405GP): - ppc4xx_pic = &ppc405_uic; - break; - } - - return; -} - -/* - * XXX - Currently 403-specific! - * - * Document me. - */ int -ppc4xx_pic_get_irq(struct pt_regs *regs) +ppc403_pic_get_irq(struct pt_regs *regs) { int irq; - unsigned long bits, mask = (1 << 31); + unsigned long bits; /* * Only report the status of those interrupts that are actually @@ -120,19 +92,17 @@ /* * Walk through the interrupts from highest priority to lowest, and * report the first pending interrupt found. + * We want PPC, not C bit numbering, so just subtract the ffs() + * result from 32. */ + irq = 32 - ffs(bits); - for (irq = 0; irq < NR_IRQS; irq++, mask >>= 1) { - if (bits & mask) - break; - } + if (irq == NR_AIC_IRQS) + irq = -1; return (irq); } -/* - * Document me. - */ static void ppc403_aic_enable(unsigned int irq) { @@ -145,9 +115,6 @@ mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]); } -/* - * Document me. - */ static void ppc403_aic_disable(unsigned int irq) { @@ -160,9 +127,6 @@ mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]); } -/* - * Document me. - */ static void ppc403_aic_disable_and_ack(unsigned int irq) { @@ -176,29 +140,308 @@ mtdcr(DCRN_EXISR, (1 << (31 - bit))); } -/* - * Document me. - */ +#else + +#ifndef UIC1 +#define UIC1 UIC0 +#endif + static void ppc405_uic_enable(unsigned int irq) { - /* XXX - Implement me. */ -} + int bit, word; + irq_desc_t *desc = irq_desc + irq; -/* - * Document me. + bit = irq & 0x1f; + word = irq >> 5; + +#ifdef UIC_DEBUG + printk("ppc405_uic_enable - irq %d word %d bit 0x%x\n", irq, word, bit); +#endif + ppc_cached_irq_mask[word] |= 1 << (31 - bit); + switch (word) { + case 0: + mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]); + if ((mfdcr(DCRN_UIC_TR(UIC0)) & (1 << (31 - bit))) == 0) + desc->status |= IRQ_LEVEL; + else + /* lets hope this works since in linux/irq.h + * there is no define for EDGE and it's assumed + * once you set status to LEVEL you would not + * want to change it - Armin + */ + desc->status = desc->status & ~IRQ_LEVEL; + break; + case 1: + mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]); + if ((mfdcr(DCRN_UIC_TR(UIC1)) & (1 << (31 - bit))) == 0) + desc->status |= IRQ_LEVEL; + else + /* lets hope this works since in linux/irq.h + * there is no define for EDGE and it's assumed + * once you set status to LEVEL you would not + * want to change it - Armin */ + desc->status = desc->status & ~IRQ_LEVEL; + break; + } + +} + static void ppc405_uic_disable(unsigned int irq) { - /* XXX - Implement me. */ + int bit, word; + + bit = irq & 0x1f; + word = irq >> 5; +#ifdef UIC_DEBUG + printk("ppc405_uic_disable - irq %d word %d bit 0x%x\n", irq, word, + bit); +#endif + ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); + switch (word) { + case 0: + mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]); + break; + case 1: + mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]); + break; + } } -/* - * Document me. - */ static void ppc405_uic_disable_and_ack(unsigned int irq) { - /* XXX - Implement me. */ + int bit, word; + + bit = irq & 0x1f; + word = irq >> 5; + +#ifdef UIC_DEBUG + printk("ppc405_uic_disable_and_ack - irq %d word %d bit 0x%x\n", irq, + word, bit); +#endif + ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); + switch (word) { + case 0: + mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]); + mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - bit))); + break; +#if NR_UICS > 1 + case 1: + mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]); + mtdcr(DCRN_UIC_SR(UIC1), (1 << (31 - bit))); + /* ACK cascaded interrupt in UIC0 */ + mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - UIC0_UIC1NC))); + break; +#endif + } +} + +static void +ppc405_uic_end(unsigned int irq) +{ + int bit, word; + unsigned int tr_bits; + + bit = irq & 0x1f; + word = irq >> 5; + +#ifdef UIC_DEBUG + printk("ppc405_uic_end - irq %d word %d bit 0x%x\n", irq, word, bit); +#endif + + switch (word) { + case 0: + tr_bits = mfdcr(DCRN_UIC_TR(UIC0)); + break; + case 1: + tr_bits = mfdcr(DCRN_UIC_TR(UIC1)); + break; + } + + if ((tr_bits & (1 << (31 - bit))) == 0) { + /* level trigger */ + switch (word) { + case 0: + mtdcr(DCRN_UIC_SR(UIC0), 1 << (31 - bit)); + break; +#if NR_UICS > 1 + case 1: + mtdcr(DCRN_UIC_SR(UIC1), 1 << (31 - bit)); + /* ACK cascaded interrupt in UIC0 */ + mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - UIC0_UIC1NC))); + break; +#endif + } + } + + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + ppc_cached_irq_mask[word] |= 1 << (31 - bit); + switch (word) { + case 0: + mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]); + break; + case 1: + mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]); + break; + } + } +} + +static struct hw_interrupt_type ppc405_uic = { +#if (NR_UICS == 1) + "IBM UIC", +#else + "IBM UIC Cascade", +#endif + NULL, + NULL, + ppc405_uic_enable, + ppc405_uic_disable, + ppc405_uic_disable_and_ack, + ppc405_uic_end, + 0 +}; + +int +ppc405_pic_get_irq(struct pt_regs *regs) +{ + int irq, cas_irq; + unsigned long bits; + cas_irq = 0; + /* + * Only report the status of those interrupts that are actually + * enabled. + */ + + bits = mfdcr(DCRN_UIC_MSR(UIC0)); + +#if (NR_UICS > 1) + if (bits & UIC_CASCADE_MASK) { + bits = mfdcr(DCRN_UIC_MSR(UIC1)); + cas_irq = 32 - ffs(bits); + irq = 32 + cas_irq; + } else { + irq = 32 - ffs(bits); + if (irq == 32) + irq = -1; + } +#else + /* + * Walk through the interrupts from highest priority to lowest, and + * report the first pending interrupt found. + * We want PPC, not C bit numbering, so just subtract the ffs() + * result from 32. + */ + irq = 32 - ffs(bits); +#endif + if (irq == (NR_UIC_IRQS * NR_UICS)) + irq = -1; + +#ifdef UIC_DEBUG + printk("ppc405_pic_get_irq - irq %d bit 0x%x\n", irq, bits); +#endif + + return (irq); +} +#endif + +void __init +ppc4xx_extpic_init(void) +{ + unsigned int sense, irq; + int bit, word; + unsigned long ppc_cached_sense_mask[NR_MASK_WORDS]; + unsigned long ppc_cached_pol_mask[NR_MASK_WORDS]; + ppc_cached_sense_mask[0] = 0; + ppc_cached_sense_mask[1] = 0; + ppc_cached_pol_mask[0] = 0; + ppc_cached_pol_mask[1] = 0; + + for (irq = 0; irq < NR_IRQS; irq++) { + + bit = irq & 0x1f; + word = irq >> 5; + + sense = (irq < ibm4xxPIC_NumInitSenses) ? + ibm4xxPIC_InitSenses[irq] : + IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE; +#ifdef PPC4xx_PIC_DEBUG + printk("PPC4xx_picext %d word:%x bit:%x sense:%x", irq, word, + bit, sense); +#endif + ppc_cached_sense_mask[word] |= + (~sense & IRQ_SENSE_MASK) << (31 - bit); + ppc_cached_pol_mask[word] |= + ((sense & IRQ_POLARITY_MASK) >> 1) << (31 - bit); + switch (word) { + case 0: +#ifdef PPC4xx_PIC_DEBUG + printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC0))); + printk("Level %x\n", mfdcr(DCRN_UIC_TR(UIC0))); +#endif + /* polarity setting */ + mtdcr(DCRN_UIC_PR(UIC0), ppc_cached_pol_mask[word]); + + /* Level setting */ + mtdcr(DCRN_UIC_TR(UIC0), ppc_cached_sense_mask[word]); + + break; + case 1: +#ifdef PPC4xx_PIC_DEBUG + printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC1))); + printk("Level %x\n", mfdcr(DCRN_UIC_TR(UIC1))); +#endif + /* polarity setting */ + mtdcr(DCRN_UIC_PR(UIC1), ppc_cached_pol_mask[word]); + + /* Level setting */ + mtdcr(DCRN_UIC_TR(UIC1), ppc_cached_sense_mask[word]); + + break; + } + } + +} +void __init +ppc4xx_pic_init(void) +{ + + /* + * Disable all external interrupts until they are + * explicity requested. + */ + ppc_cached_irq_mask[0] = 0; + ppc_cached_irq_mask[1] = 0; + +#if defined CONFIG_403 + mtdcr(DCRN_EXIER, ppc_cached_irq_mask[0]); + + ppc4xx_pic = &ppc403_aic; + ppc_md.get_irq = ppc403_pic_get_irq; +#else +#if (NR_UICS > 1) + ppc_cached_irq_mask[0] |= 1 << (31 - UIC0_UIC1NC); /* enable cascading interrupt */ + mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[1]); + mtdcr(DCRN_UIC_CR(UIC1), 0); + +#endif + mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]); + mtdcr(DCRN_UIC_CR(UIC0), 0); + + if (ibm4xxPIC_InitSenses != NULL) + ppc4xx_extpic_init(); + + /* Clear any pending interrupts */ +#if (NR_UICS > 1) + mtdcr(DCRN_UIC_SR(UIC1), 0xffffffff); +#endif + mtdcr(DCRN_UIC_SR(UIC0), 0xffffffff); + + ppc4xx_pic = &ppc405_uic; + ppc_md.get_irq = ppc405_pic_get_irq; +#endif + } diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/ppc4xx_setup.c cset-v2.4.20/arch/ppc/kernel/ppc4xx_setup.c --- cset-v2.4.20~/arch/ppc/kernel/ppc4xx_setup.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/ppc4xx_setup.c 2004-11-01 22:35:09.000000000 +0900 @@ -0,0 +1,431 @@ +/* + * + * Copyright (c) 1999-2000 Grant Erickson + * + * Copyright 2000-2002 MontaVista Software Inc. + * Completed implementation. + * Author: MontaVista Software, Inc. + * Frank Rowand + * Debbie Chu + * + * Module name: ppc4xx_setup.c + * + * Description: + * Architecture- / platform-specific boot-time initialization code for + * IBM PowerPC 4xx based boards. Adapted from original + * code by Gary Thomas, Cort Dougan , and Dan Malek + * . + * + * History: 11/09/2001 - armin + * rename board_setup_nvram_access to board_init. board_init is + * used for all other board specific instructions needed during + * platform_init. + * moved RTC to board.c files + * moved VT/FB to board.c files + * moved r/w4 ide to redwood.c + * + * History: 04/18/02 - Armin + * added ash to setting CETE bit in calibrate() + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Function Prototypes */ +static void ppc4xx_gdb_init(void); + +extern void abort(void); +extern void ppc4xx_find_bridges(void); + +extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode); +extern int pckbd_getkeycode(unsigned int scancode); +extern int pckbd_pretranslate(unsigned char scancode, char raw_mode); +extern int pckbd_translate(unsigned char scancode, unsigned char *keycode, + char raw_mode); +extern char pckbd_unexpected_up(unsigned char keycode); +extern void pckbd_leds(unsigned char leds); +extern void pckbd_init_hw(void); + +extern int nonpci_ide_default_irq(ide_ioreg_t base); +extern void nonpci_ide_init_hwif_ports(hw_regs_t * hw, ide_ioreg_t data_port, + ide_ioreg_t ctrl_port, int *irq); + +extern void ppc4xx_wdt_heartbeat(void); +extern int wdt_enable; +extern unsigned long wdt_period; +//extern void early_uart_init(void); + +/* Board specific functions */ +extern void board_setup_arch(void); +extern void board_io_mapping(void); +extern void board_setup_irq(void); +extern void board_init(void); + +/* Global Variables */ +unsigned char __res[sizeof (bd_t)]; + +#if defined(EMAC_NUMS) && EMAC_NUMS > 0 +u32 emac_phy_map[EMAC_NUMS]; +EXPORT_SYMBOL(emac_phy_map); +#endif + +static void __init +ppc4xx_setup_arch(void) +{ + + /* Setup PCI host bridges */ + +#ifdef CONFIG_PCI + ppc4xx_find_bridges(); +#endif + +#if defined(CONFIG_FB) + conswitchp = &dummy_con; +#endif +#if defined (CONFIG_SERIAL) && !defined (CONFIG_RAINIER) +// early_uart_init(); +#endif + board_setup_arch(); + + ppc4xx_gdb_init(); +} + +/* + * This routine pretty-prints the platform's internal CPU clock + * frequencies into the buffer for usage in /proc/cpuinfo. + */ + +static int +ppc4xx_show_percpuinfo(struct seq_file *m, int i) +{ + bd_t *bip = (bd_t *) __res; + + seq_printf(m, "clock\t\t: %ldMHz\n", (long) bip->bi_intfreq / 1000000); + + return 0; +} + +/* + * This routine pretty-prints the platform's internal bus clock + * frequencies into the buffer for usage in /proc/cpuinfo. + */ +static int +ppc4xx_show_cpuinfo(struct seq_file *m) +{ + bd_t *bip = (bd_t *) __res; + + seq_printf(m, "machine\t\t: %s\n", PPC4xx_MACHINE_NAME); + seq_printf(m, "plb bus clock\t: %ldMHz\n", + (long) bip->bi_busfreq / 1000000); +#ifdef CONFIG_PCI + seq_printf(m, "pci bus clock\t: %dMHz\n", + bip->bi_pci_busfreq / 1000000); +#endif + + return 0; +} + +/* + * Return the virtual address representing the top of physical RAM. + */ +static unsigned long __init +ppc4xx_find_end_of_memory(void) +{ + bd_t *bip = (bd_t *) __res; + + return ((unsigned long) bip->bi_memsize); +} + +static void __init +m4xx_map_io(void) +{ + io_block_mapping(PPC4xx_ONB_IO_VADDR, + PPC4xx_ONB_IO_PADDR, PPC4xx_ONB_IO_SIZE, _PAGE_IO); +#ifdef CONFIG_PCI + io_block_mapping(PPC4xx_PCI_IO_VADDR, + PPC4xx_PCI_IO_PADDR, PPC4xx_PCI_IO_SIZE, _PAGE_IO); + io_block_mapping(PPC4xx_PCI_CFG_VADDR, + PPC4xx_PCI_CFG_PADDR, PPC4xx_PCI_CFG_SIZE, _PAGE_IO); + io_block_mapping(PPC4xx_PCI_LCFG_VADDR, + PPC4xx_PCI_LCFG_PADDR, PPC4xx_PCI_LCFG_SIZE, _PAGE_IO); +#endif + board_io_mapping(); +} + +static void __init +ppc4xx_init_IRQ(void) +{ + int i; + + ppc4xx_pic_init(); + + for (i = 0; i < NR_IRQS; i++) + irq_desc[i].handler = ppc4xx_pic; + + /* give board specific code a chance to setup things */ + board_setup_irq(); + return; +} + +static void +ppc4xx_restart(char *cmd) +{ + printk("%s\n", cmd); + abort(); +} + +static void +ppc4xx_halt(void) +{ + printk("System Halted\n"); + __cli(); + while (1) ; +} + +static void __init +ppc4xx_gdb_init(void) +{ +#if !defined(CONFIG_BDI_SWITCH) + /* + * The Abatron BDI JTAG debugger does not tolerate others + * mucking with the debug registers. + */ + mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM)); + mtspr(SPRN_DBCR1, 0); +#endif +} + +/* + * This routine retrieves the internal processor frequency from the board + * information structure, sets up the kernel timer decrementer based on + * that value, enables the 4xx programmable interval timer (PIT) and sets + * it up for auto-reload. + */ +static void __init +ppc4xx_calibrate_decr(void) +{ + unsigned int freq; + bd_t *bip = (bd_t *) __res; + +#if defined(CONFIG_WALNUT) || defined(CONFIG_CEDER) \ + || defined(CONFIG_ASH) || defined(CONFIG_SYCAMORE) + /* Openbios sets cpu timers to CPU clk + * we want to use the external clk + * DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */ + + mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE); +#endif + + freq = bip->bi_tbfreq; +// tb_ticks_per_jiffy = freq / HZ; +// tb_to_us = mulhwu_scale_factor(freq, 1000000); + tb_ticks_per_jiffy = (freq + HZ/2) / HZ; + tb_to_us = mulhwu_scale_factor(tb_ticks_per_jiffy*HZ, 1000000U); + + /* Set the time base to zero. + ** At 200 Mhz, time base will rollover in ~2925 years. + */ + + mtspr(SPRN_TBWL, 0); + mtspr(SPRN_TBWU, 0); + + /* Clear any pending timer interrupts */ + + mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_PIS | TSR_FIS); + mtspr(SPRN_TCR, TCR_PIE | TCR_ARE); + + /* Set the PIT reload value and just let it run. */ + mtspr(SPRN_PIT, tb_ticks_per_jiffy); +} + +#ifdef CONFIG_SERIAL_TEXT_DEBUG + +/* We assume that the UART has already been initialized by the + firmware or the boot loader */ +static void +serial_putc(u8 * com_port, unsigned char c) +{ + while ((readb(com_port + (UART_LSR)) & UART_LSR_THRE) == 0) ; + writeb(c, com_port); +} + +static void +ppc4xx_progress(char *s, unsigned short hex) +{ + char c; +#ifdef SERIAL_DEBUG_IO_BASE + u8 *com_port = (u8 *) SERIAL_DEBUG_IO_BASE; + + while ((c = *s++) != '\0') { + serial_putc(com_port, c); + } + serial_putc(com_port, '\r'); + serial_putc(com_port, '\n'); +#else + printk("%s\r\n", s); +#endif +} +#endif /* CONFIG_SERIAL_TEXT_DEBUG */ + +/* + * IDE stuff. + * should be generic for every IDE PCI chipset + */ +#if defined(CONFIG_BLK_DEV_IDEPCI) +static void +ppc4xx_ide_init_hwif_ports(hw_regs_t * hw, ide_ioreg_t data_port, + ide_ioreg_t ctrl_port, int *irq) +{ + int i; + + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i) + hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET; + + hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; +} +#endif + +TODC_ALLOC(); + +/* + * Input(s): + * r3 - Optional pointer to a board information structure. + * r4 - Optional pointer to the physical starting address of the init RAM + * disk. + * r5 - Optional pointer to the physical ending address of the init RAM + * disk. + * r6 - Optional pointer to the physical starting address of any kernel + * command-line parameters. + * r7 - Optional pointer to the physical ending address of any kernel + * command-line parameters. + */ +void __init +platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + parse_bootinfo(find_bootinfo()); + + /* + * If we were passed in a board information, copy it into the + * residual data area. + */ + if (r3) { + memcpy((void *) __res, (void *) (r3 + KERNELBASE), + sizeof (bd_t)); + + } +#if defined(CONFIG_BLK_DEV_INITRD) + /* + * If the init RAM disk has been configured in, and there's a valid + * starting address for it, set it up. + */ + if (r4) { + initrd_start = r4 + KERNELBASE; + initrd_end = r5 + KERNELBASE; + } +#endif /* CONFIG_BLK_DEV_INITRD */ + + /* Copy the kernel command line arguments to a safe place. */ + + if (r6) { + *(char *) (r7 + KERNELBASE) = 0; + strcpy(cmd_line, (char *) (r6 + KERNELBASE)); + } +#if defined(CONFIG_PPC405_WDT) + ppc_md.heartbeat = ppc4xx_wdt_heartbeat; + +/* Look for wdt= option on command line */ + if (strstr(cmd_line, "wdt=")) { + int valid_wdt = 0; + char *p, *q; + for (q = cmd_line; (p = strstr(q, "wdt=")) != 0;) { + q = p + 4; + if (p > cmd_line && p[-1] != ' ') + continue; + wdt_period = simple_strtoul(q, &q, 0); + valid_wdt = 1; + ++q; + } + wdt_enable = valid_wdt; + } +#endif + + /* Initialize machine-dependency vectors */ + + ppc_md.setup_arch = ppc4xx_setup_arch; + ppc_md.show_percpuinfo = ppc4xx_show_percpuinfo; + ppc_md.show_cpuinfo = ppc4xx_show_cpuinfo; + ppc_md.init_IRQ = ppc4xx_init_IRQ; + + ppc_md.restart = ppc4xx_restart; + ppc_md.power_off = ppc4xx_halt; + ppc_md.halt = ppc4xx_halt; + + ppc_md.calibrate_decr = ppc4xx_calibrate_decr; + + ppc_md.find_end_of_memory = ppc4xx_find_end_of_memory; + ppc_md.setup_io_mappings = m4xx_map_io; + +#ifdef CONFIG_SERIAL_TEXT_DEBUG + ppc_md.progress = ppc4xx_progress; +#endif +#ifdef CONFIG_KGDB +// ppc_md.early_serial_map = early_uart_init; +#endif +#if defined(CONFIG_VT) && defined(CONFIG_PC_KEYBOARD) +#if defined(CONFIG_REDWOOD_4) && defined(CONFIG_STB_KB) + redwood_irkb_init(); +#else + ppc_md.kbd_setkeycode = pckbd_setkeycode; + ppc_md.kbd_getkeycode = pckbd_getkeycode; + ppc_md.kbd_translate = pckbd_translate; + ppc_md.kbd_unexpected_up = pckbd_unexpected_up; + ppc_md.kbd_leds = pckbd_leds; + ppc_md.kbd_init_hw = pckbd_init_hw; +#endif +#endif + +/* +** m8xx_setup.c, prep_setup.c use +** defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) +*/ +#if defined (CONFIG_IDE) +#if defined(CONFIG_BLK_DEV_IDEPCI) + ppc_ide_md.ide_init_hwif = ppc4xx_ide_init_hwif_ports; +#elif defined (CONFIG_DMA_NONPCI) /* ON board IDE */ + ppc_ide_md.default_irq = nonpci_ide_default_irq; + ppc_ide_md.ide_init_hwif = nonpci_ide_init_hwif_ports; +#endif +#endif + board_init(); + + return; +} diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/ppc_ksyms.c cset-v2.4.20/arch/ppc/kernel/ppc_ksyms.c --- cset-v2.4.20~/arch/ppc/kernel/ppc_ksyms.c 2004-10-25 15:06:06.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/ppc_ksyms.c 2004-11-01 22:35:09.000000000 +0900 @@ -161,11 +161,14 @@ EXPORT_SYMBOL(_outsw_ns); EXPORT_SYMBOL(_insl_ns); EXPORT_SYMBOL(_outsl_ns); +EXPORT_SYMBOL(iopa); +EXPORT_SYMBOL(mm_ptov); EXPORT_SYMBOL(ioremap); +#ifdef CONFIG_44x +EXPORT_SYMBOL(ioremap64); +#endif EXPORT_SYMBOL(__ioremap); EXPORT_SYMBOL(iounmap); -EXPORT_SYMBOL(iopa); -EXPORT_SYMBOL(mm_ptov); #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) \ || defined(CONFIG_USB_STORAGE) || defined(CONFIG_USB_STORAGE_MODULE) @@ -179,8 +182,23 @@ EXPORT_SYMBOL_NOVERS(pci_dram_offset); EXPORT_SYMBOL(pci_alloc_consistent); EXPORT_SYMBOL(pci_free_consistent); +EXPORT_SYMBOL(pci_bus_io_base); +EXPORT_SYMBOL(pci_bus_io_base_phys); +EXPORT_SYMBOL(pci_bus_mem_base_phys); +EXPORT_SYMBOL(pci_bus_to_hose); +EXPORT_SYMBOL(pci_resource_to_bus); +EXPORT_SYMBOL(pci_phys_to_bus); +EXPORT_SYMBOL(pci_bus_to_phys); #endif /* CONFIG_PCI */ +#ifdef CONFIG_NOT_COHERENT_CACHE +EXPORT_SYMBOL(consistent_alloc); +EXPORT_SYMBOL(consistent_free); +EXPORT_SYMBOL(consistent_sync); +EXPORT_SYMBOL(consistent_sync_page); +EXPORT_SYMBOL(flush_dcache_all); +#endif + EXPORT_SYMBOL(start_thread); EXPORT_SYMBOL(kernel_thread); @@ -256,15 +274,8 @@ EXPORT_SYMBOL(get_property); EXPORT_SYMBOL(request_OF_resource); EXPORT_SYMBOL(release_OF_resource); -EXPORT_SYMBOL(pci_bus_io_base); -EXPORT_SYMBOL(pci_bus_io_base_phys); -EXPORT_SYMBOL(pci_bus_mem_base_phys); EXPORT_SYMBOL(pci_device_to_OF_node); EXPORT_SYMBOL(pci_device_from_OF_node); -EXPORT_SYMBOL(pci_bus_to_hose); -EXPORT_SYMBOL(pci_resource_to_bus); -EXPORT_SYMBOL(pci_phys_to_bus); -EXPORT_SYMBOL(pci_bus_to_phys); EXPORT_SYMBOL(pmac_newworld); EXPORT_SYMBOL(nvram_read_byte); EXPORT_SYMBOL(nvram_write_byte); @@ -294,7 +305,7 @@ EXPORT_SYMBOL(abs); -#ifdef CONFIG_VGA_CONSOLE +#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_FB) EXPORT_SYMBOL(screen_info); #endif @@ -341,8 +352,10 @@ EXPORT_SYMBOL(debugger_fault_handler); #endif -#ifdef CONFIG_8xx +#if defined(CONFIG_8xx) || defined(CONFIG_4xx) EXPORT_SYMBOL(__res); +#endif +#ifdef CONFIG_8xx EXPORT_SYMBOL(request_8xxirq); EXPORT_SYMBOL(cpm_install_handler); EXPORT_SYMBOL(cpm_free_handler); diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/process.c cset-v2.4.20/arch/ppc/kernel/process.c --- cset-v2.4.20~/arch/ppc/kernel/process.c 2004-10-25 15:04:20.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/process.c 2004-11-01 22:35:09.000000000 +0900 @@ -252,20 +252,33 @@ regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, regs->msr&MSR_IR ? 1 : 0, regs->msr&MSR_DR ? 1 : 0); +#ifdef CONFIG_4xx + /* + * TRAP 0x800 is the hijacked FPU unavailable exception vector + * on 40x used to implement the heavyweight data access + * functionality. It is an emulated value (like all trap + * vectors) on 440. + */ + if (regs->trap == 0x300 || regs->trap == 0x600 || regs->trap == 0x800) + printk("DEAR: %08lX, ESR: %08lX\n", regs->dar, regs->dsisr); +#else if (regs->trap == 0x300 || regs->trap == 0x600) printk("DAR: %08lX, DSISR: %08lX\n", regs->dar, regs->dsisr); +#endif printk("TASK = %p[%d] '%s' ", current, current->pid, current->comm); printk("Last syscall: %ld ", current->thread.last_syscall); printk("\nlast math %p last altivec %p", last_task_used_math, last_task_used_altivec); -#ifdef CONFIG_4xx +#if defined(CONFIG_4xx) && defined(DCRN_PLB0_BEAR) printk("\nPLB0: bear= 0x%8.8x acr= 0x%8.8x besr= 0x%8.8x\n", - mfdcr(DCRN_POB0_BEAR), mfdcr(DCRN_PLB0_ACR), + mfdcr(DCRN_PLB0_BEAR), mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESR)); +#endif +#if defined(CONFIG_4xx) && defined(DCRN_POB0_BEAR) printk("PLB0 to OPB: bear= 0x%8.8x besr0= 0x%8.8x besr1= 0x%8.8x\n", - mfdcr(DCRN_PLB0_BEAR), mfdcr(DCRN_POB0_BESR0), + mfdcr(DCRN_POB0_BEAR), mfdcr(DCRN_POB0_BESR0), mfdcr(DCRN_POB0_BESR1)); #endif diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/ptrace.c cset-v2.4.20/arch/ppc/kernel/ptrace.c --- cset-v2.4.20~/arch/ppc/kernel/ptrace.c 2004-10-25 15:01:46.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/ptrace.c 2004-11-01 22:35:09.000000000 +0900 @@ -36,7 +36,11 @@ /* * Set of msr bits that gdb can change on behalf of a process. */ +#if defined(CONFIG_4xx) +#define MSR_DEBUGCHANGE (0) +#else #define MSR_DEBUGCHANGE (MSR_FE0 | MSR_SE | MSR_BE | MSR_FE1) +#endif /* * does not yet catch signals sent when the child dies. @@ -132,18 +136,27 @@ set_single_step(struct task_struct *task) { struct pt_regs *regs = task->thread.regs; - +#if defined(CONFIG_4xx) + regs->msr |= MSR_DE; + task->thread.dbcr0 |= (DBCR0_IDM | DBCR0_IC); +#else if (regs != NULL) regs->msr |= MSR_SE; +#endif + } static inline void clear_single_step(struct task_struct *task) { struct pt_regs *regs = task->thread.regs; - +#if defined(CONFIG_4xx) + regs->msr &= ~MSR_DE; + task->thread.dbcr0 &= ~DBCR0_IC; +#else if (regs != NULL) regs->msr &= ~MSR_SE; +#endif } /* @@ -278,6 +291,12 @@ child->exit_code = data; /* make sure the single step bit is not set. */ clear_single_step(child); +#ifdef CONFIG_4xx + /* ...but traps may be set, so catch those.... + */ + child->thread.regs->msr |= MSR_DE; + child->thread.dbcr0 |= (DBCR0_IDM | DBCR0_TDE); +#endif wake_up_process(child); ret = 0; break; diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/kernel/traps.c cset-v2.4.20/arch/ppc/kernel/traps.c --- cset-v2.4.20~/arch/ppc/kernel/traps.c 2004-10-25 15:01:03.000000000 +0900 +++ cset-v2.4.20/arch/ppc/kernel/traps.c 2004-11-02 17:38:17.000000000 +0900 @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.traps.c 1.22 10/11/01 10:33:09 paulus + * BK Id: %F% %I% %G% %U% %#% */ /* * linux/arch/ppc/kernel/traps.c @@ -38,6 +38,9 @@ #include #include #include +#ifdef CONFIG_PMAC_BACKLIGHT +#include +#endif extern int fix_alignment(struct pt_regs *); extern void bad_page_fault(struct pt_regs *, unsigned long, int sig); @@ -66,6 +69,13 @@ int (*debugger_iabr_match)(struct pt_regs *regs); int (*debugger_dabr_match)(struct pt_regs *regs); void (*debugger_fault_handler)(struct pt_regs *regs); +#else +#define debugger(regs) do { } while (0) +#define debugger_bpt(regs) 0 +#define debugger_sstep(regs) 0 +#define debugger_iabr_match(regs) 0 +#define debugger_dabr_match(regs) 0 +#define debugger_fault_handler ((void (*)(struct pt_regs *))0) #endif #endif @@ -74,15 +84,19 @@ */ -spinlock_t oops_lock = SPIN_LOCK_UNLOCKED; +spinlock_t die_lock = SPIN_LOCK_UNLOCKED; void die(const char * str, struct pt_regs * fp, long err) { console_verbose(); - spin_lock_irq(&oops_lock); + spin_lock_irq(&die_lock); +#ifdef CONFIG_PMAC_BACKLIGHT + set_backlight_enable(1); + set_backlight_level(BACKLIGHT_MAX); +#endif printk("Oops: %s, sig: %ld\n", str, err); show_regs(fp); - spin_unlock_irq(&oops_lock); + spin_unlock_irq(&die_lock); /* do_exit() should take care of panic'ing from an interrupt * context so we don't handle it here */ @@ -90,44 +104,21 @@ } void -_exception(int signr, struct pt_regs *regs) -{ - if (!user_mode(regs)) +_exception(int signr, struct pt_regs *regs, int code, unsigned long addr) { -#if defined(CONFIG_XMON) || defined(CONFIG_KGDB) + siginfo_t info; + + if (!user_mode(regs)) { debugger(regs); -#endif die("Exception in kernel mode", regs, signr); } - force_sig(signr, current); -} - -void -MachineCheckException(struct pt_regs *regs) -{ -#ifdef CONFIG_ALL_PPC - unsigned long fixup; -#endif /* CONFIG_ALL_PPC */ - unsigned long msr = regs->msr; - - if (user_mode(regs)) { - _exception(SIGSEGV, regs); - return; - } - -#if defined(CONFIG_8xx) && defined(CONFIG_PCI) - /* the qspan pci read routines can cause machine checks -- Cort */ - bad_page_fault(regs, regs->dar, SIGBUS); - return; -#endif -#if defined(CONFIG_XMON) || defined(CONFIG_KGDB) - if (debugger_fault_handler) { - debugger_fault_handler(regs); - return; + info.si_signo = signr; + info.si_errno = 0; + info.si_code = code; + info.si_addr = (void *) addr; + force_sig_info(signr, &info, current); } -#endif -#ifdef CONFIG_ALL_PPC /* * I/O accesses can cause machine checks on powermacs. * Check if the NIP corresponds to the address of a sync @@ -135,9 +126,15 @@ * table. * Note that the 601 only takes a machine check on TEA * (transfer error ack) signal assertion, and does not - * set of the top 16 bits of SRR1. + * set any of the top 16 bits of SRR1. * -- paulus. */ +static inline int check_io_access(struct pt_regs *regs) +{ +#ifdef CONFIG_ALL_PPC + unsigned long fixup; + unsigned long msr = regs->msr; + if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) && (fixup = search_exception_table(regs->nip)) != 0) { /* @@ -163,18 +160,101 @@ (*nip & 0x100)? "OUT to": "IN from", regs->gpr[rb] - _IO_BASE, nip); regs->nip = fixup; - return; + return 1; } } #endif /* CONFIG_ALL_PPC */ + return 0; +} + +#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) +/* On 4xx, the reason for the machine check or program exception + is in the ESR. */ +#define get_reason(regs) ((regs)->dsisr) +#define REASON_FP 0 +#define REASON_ILLEGAL ESR_PIL +#define REASON_PRIVILEGED ESR_PPR +#define REASON_TRAP ESR_PTR + +#else +/* On non-4xx, the reason for the machine check or program + exception is in the MSR. */ +#define get_reason(regs) ((regs)->msr) +#define REASON_FP 0x100000 +#define REASON_ILLEGAL 0x80000 +#define REASON_PRIVILEGED 0x40000 +#define REASON_TRAP 0x20000 +#endif + +void +MachineCheckException(struct pt_regs *regs) +{ + unsigned long reason = get_reason(regs); + + if (user_mode(regs)) { + _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); + return; + } + +#if defined(CONFIG_8xx) && defined(CONFIG_PCI) + /* the qspan pci read routines can cause machine checks -- Cort */ + bad_page_fault(regs, regs->dar, SIGBUS); + return; +#endif + if (debugger_fault_handler) { + debugger_fault_handler(regs); + return; + } + if (check_io_access(regs)) + return; + +#if defined(CONFIG_4xx) && !defined(CONFIG_440A) + if (reason & ESR_IMCP) { + printk("Instruction"); + mtspr(SPRN_ESR, reason & ~ESR_IMCP); + } else + printk("Data"); + printk(" machine check in kernel mode.\n"); +#elif defined(CONFIG_440A) + printk("Machine check in kernel mode.\n"); + if (reason & ESR_IMCP){ + printk("Instruction Synchronous Machine Check exception\n"); + mtspr(SPRN_ESR, reason & ~ESR_IMCP); + } + else { + u32 mcsr = mfspr(SPRN_MCSR); + if (mcsr & MCSR_IB) + printk("Instruction Read PLB Error\n"); + if (mcsr & MCSR_DRB) + printk("Data Read PLB Error\n"); + if (mcsr & MCSR_DWB) + printk("Data Write PLB Error\n"); + if (mcsr & MCSR_TLBP) + printk("TLB Parity Error\n"); + if (mcsr & MCSR_ICP){ + flush_instruction_cache(); + printk("I-Cache Parity Error\n"); + } + if (mcsr & MCSR_DCSP) + printk("D-Cache Search Parity Error\n"); + if (mcsr & MCSR_DCFP) + printk("D-Cache Flush Parity Error\n"); + if (mcsr & MCSR_IMPE) + printk("Machine Check exception is imprecise\n"); + + /* Clear MCSR */ + mtspr(SPRN_MCSR, mcsr); + } +#else /* !CONFIG_4xx && !CONFIG_E500 */ printk("Machine check in kernel mode.\n"); - printk("Caused by (from SRR1=%lx): ", msr); - switch (msr & 0xF0000) { + printk("Caused by (from SRR1=%lx): ", reason); + switch (reason & 0x601F0000) { case 0x80000: printk("Machine check signal\n"); break; case 0: /* for 601 */ case 0x40000: + case 0x140000: /* 7450 MSS error and TEA */ printk("Transfer error ack signal\n"); break; case 0x20000: @@ -183,26 +263,32 @@ case 0x10000: printk("Address parity error signal\n"); break; + case 0x20000000: + printk("L1 Data Cache error\n"); + break; + case 0x40000000: + printk("L1 Instruction Cache error\n"); + break; + case 0x00100000: + printk("L2 data cache parity error\n"); + break; default: printk("Unknown values in msr\n"); } -#if defined(CONFIG_XMON) || defined(CONFIG_KGDB) +#endif /* CONFIG_4xx */ + debugger(regs); -#endif die("machine check", regs, SIGBUS); } void SMIException(struct pt_regs *regs) { -#if defined(CONFIG_XMON) || defined(CONFIG_KGDB) - { debugger(regs); - return; - } -#endif +#if !(defined(CONFIG_XMON) || defined(CONFIG_KGDB)) show_regs(regs); panic("System Management Interrupt"); +#endif } void @@ -210,23 +296,21 @@ { printk("Bad trap at PC: %lx, SR: %lx, vector=%lx %s\n", regs->nip, regs->msr, regs->trap, print_tainted()); - _exception(SIGTRAP, regs); + _exception(SIGTRAP, regs, 0, 0); } void InstructionBreakpoint(struct pt_regs *regs) { -#if defined(CONFIG_XMON) || defined(CONFIG_KGDB) if (debugger_iabr_match(regs)) return; -#endif - _exception(SIGTRAP, regs); + _exception(SIGTRAP, regs, TRAP_BRKPT, 0); } void RunModeException(struct pt_regs *regs) { - _exception(SIGTRAP, regs); + _exception(SIGTRAP, regs, 0, 0); } /* Illegal instruction emulation support. Originally written to @@ -245,16 +329,16 @@ static int emulate_instruction(struct pt_regs *regs) { - uint instword; - uint rd; - uint retval; + u32 instword; + u32 rd; + int retval; - retval = EINVAL; + retval = -EINVAL; if (!user_mode(regs)) return retval; - if (get_user(instword, (uint *)(regs->nip))) + if (get_user(instword, (u32 *)(regs->nip))) return -EFAULT; /* Emulate the mfspr rD, PVR. @@ -263,60 +347,78 @@ rd = (instword >> 21) & 0x1f; regs->gpr[rd] = mfspr(PVR); retval = 0; - } - if (retval == 0) regs->nip += 4; - return(retval); + } + return retval; } void ProgramCheckException(struct pt_regs *regs) { -#if defined(CONFIG_4xx) - unsigned int esr = mfspr(SPRN_ESR); + unsigned int reason = get_reason(regs); + extern int do_mathemu(struct pt_regs *regs); - if (esr & ESR_PTR) { -#if defined(CONFIG_XMON) || defined(CONFIG_KGDB) - if (debugger_bpt(regs)) +#ifdef CONFIG_MATH_EMULATION + /* (reason & REASON_ILLEGAL) would be the obvious thing here, + * but there seems to be a hardware bug on the 405GP (RevD) + * that means ESR is sometimes set incorrectly - either to + * ESR_DST (!?) or 0. In the process of chasing this with the + * hardware people - not sure if it can happen on any illegal + * instruction or only on FP instructions, whether there is a + * pattern to occurences etc. -dgibson 31/Mar/2003 */ + if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) return; -#endif - _exception(SIGTRAP, regs); - } else { - _exception(SIGILL, regs); - } -#else - if (regs->msr & 0x100000) { +#endif /* CONFIG_MATH_EMULATION */ + + if (reason & REASON_FP) { /* IEEE FP exception */ - _exception(SIGFPE, regs); - } else if (regs->msr & 0x20000) { + int code = 0; + u32 fpscr; + + if (regs->msr & MSR_FP) + giveup_fpu(current); + fpscr = current->thread.fpscr; + fpscr &= fpscr << 22; /* mask summary bits with enables */ + if (fpscr & FPSCR_VX) + code = FPE_FLTINV; + else if (fpscr & FPSCR_OX) + code = FPE_FLTOVF; + else if (fpscr & FPSCR_UX) + code = FPE_FLTUND; + else if (fpscr & FPSCR_ZX) + code = FPE_FLTDIV; + else if (fpscr & FPSCR_XX) + code = FPE_FLTRES; + _exception(SIGFPE, regs, code, regs->nip); + return; + } + + if (reason & REASON_TRAP) { /* trap exception */ -#if defined(CONFIG_XMON) || defined(CONFIG_KGDB) if (debugger_bpt(regs)) return; -#endif - _exception(SIGTRAP, regs); - } else { - /* Try to emulate it if we should. */ - int errcode; - if ((errcode = emulate_instruction(regs))) { - if (errcode == -EFAULT) - _exception(SIGBUS, regs); - else - _exception(SIGILL, regs); + _exception(SIGTRAP, regs, TRAP_BRKPT, 0); + return; } + + if (reason & REASON_PRIVILEGED) { + /* Try to emulate it if we should. */ + if (emulate_instruction(regs) == 0) + return; + _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); + return; } -#endif + + _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); } void SingleStepException(struct pt_regs *regs) { regs->msr &= ~MSR_SE; /* Turn off 'trace' bit */ -#if defined(CONFIG_XMON) || defined(CONFIG_KGDB) if (debugger_sstep(regs)) return; -#endif - _exception(SIGTRAP, regs); + _exception(SIGTRAP, regs, TRAP_TRACE, 0); } void @@ -332,12 +434,12 @@ if (fixed == -EFAULT) { /* fixed == -EFAULT means the operand address was bad */ if (user_mode(regs)) - force_sig(SIGSEGV, current); + _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar); else bad_page_fault(regs, regs->dar, SIGSEGV); return; } - _exception(SIGBUS, regs); + _exception(SIGBUS, regs, BUS_ADRALN, regs->dar); } void @@ -345,9 +447,7 @@ { printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", current, regs->gpr[1]); -#if defined(CONFIG_XMON) || defined(CONFIG_KGDB) debugger(regs); -#endif show_regs(regs); panic("kernel stack overflow"); } @@ -365,29 +465,58 @@ SoftwareEmulation(struct pt_regs *regs) { extern int do_mathemu(struct pt_regs *); + extern int Soft_emulate_8xx(struct pt_regs *); int errcode; if (!user_mode(regs)) { -#if defined(CONFIG_XMON) || defined(CONFIG_KGDB) debugger(regs); -#endif die("Kernel Mode Software FPU Emulation", regs, SIGFPE); } #ifdef CONFIG_MATH_EMULATION - if ((errcode = do_mathemu(regs))) { + errcode = do_mathemu(regs); #else - if ((errcode = Soft_emulate_8xx(regs))) { + errcode = Soft_emulate_8xx(regs); #endif + if (errcode) { if (errcode > 0) - _exception(SIGFPE, regs); + _exception(SIGFPE, regs, 0, 0); else if (errcode == -EFAULT) - _exception(SIGSEGV, regs); + _exception(SIGSEGV, regs, 0, 0); else - _exception(SIGILL, regs); + _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); } } -#endif +#endif /* CONFIG_8xx */ + +#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) + +void DebugException(struct pt_regs *regs) +{ + unsigned long debug_status; + + debug_status = mfspr(SPRN_DBSR); + + regs->msr &= ~MSR_DE; /* Turn off 'debug' bit */ + if (debug_status & DBSR_TIE) { /* trap instruction*/ + + mtspr(SPRN_DBSR, DBSR_TIE); + + if (!user_mode(regs) && debugger_bpt(regs)) + return; + _exception(SIGTRAP, regs, 0, 0); + + } else if (debug_status & DBSR_IC) { /* instruction completion */ + + mtspr(SPRN_DBSR, DBSR_IC); + current->thread.dbcr0 &= ~DBCR0_IC; + + if (!user_mode(regs) && debugger_sstep(regs)) + return; + _exception(SIGTRAP, regs, 0, 0); + } +} +#endif /* CONFIG_4xx || CONFIG_BOOKE */ #if !defined(CONFIG_TAU_INT) void diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/mm/44x_mmu.c cset-v2.4.20/arch/ppc/mm/44x_mmu.c --- cset-v2.4.20~/arch/ppc/mm/44x_mmu.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/mm/44x_mmu.c 2004-11-01 22:35:09.000000000 +0900 @@ -0,0 +1,142 @@ +/* + * Modifications by Matt Porter (mporter@mvista.com) to support + * PPC44x Book E processors. + * + * This file contains the routines for initializing the MMU + * on the 4xx series of chips. + * -- paulus + * + * Derived from arch/ppc/mm/init.c: + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) + * and Cort Dougan (PReP) (cort@cs.nmt.edu) + * Copyright (C) 1996 Paul Mackerras + * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * + * Derived from "arch/i386/mm/init.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mmu_decl.h" +#include "mem_pieces.h" + +extern char etext[], _stext[]; +extern struct mem_pieces phys_avail; + +/* Used by the 44x TLB replacement exception handler. + * Just needed it declared someplace. + */ +unsigned int tlb_44x_index = 0; +unsigned int tlb_44x_hwater = 61; + +/* + * "Pins" a 256MB TLB entry in AS0 for kernel lowmem + */ +static void __init +ppc44x_pin_tlb(int slot, unsigned int virt, unsigned int phys) +{ + unsigned long attrib; + + __asm__ __volatile__("\ + clrrwi %2,%2,10\n\ + ori %2,%2,%4\n\ + clrrwi %1,%1,10\n\ + li %0,0\n\ + ori %0,%0,%5\n\ + tlbwe %2,%3,%6\n\ + tlbwe %1,%3,%7\n\ + tlbwe %0,%3,%8" + : + : "r" (attrib), "r" (phys), "r" (virt), "r" (slot), + "i" (PPC44x_TLB_VALID | PPC44x_TLB_PAGESZ(PPC44x_PAGESZ_256M)), + "i" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G), + "i" (PPC44x_TLB_PAGEID), + "i" (PPC44x_TLB_XLAT), + "i" (PPC44x_TLB_ATTRIB)); +} + +/* + * Configure PPC44x TLB for AS0 exception processing. + */ +static void __init +ppc44x_tlb_config(void) +{ + unsigned int pinned_tlbs = 1; + int i; + + /* + * If lowmem is not on a pin tlb entry size boundary, + * then reserve the last page of system memory. This + * eliminates the possibility of a speculative dcache + * fetch past the end of system memory that would + * result in a machine check exception. + */ + if (total_lowmem & (PPC44x_PIN_SIZE - 1)) + mem_pieces_remove(&phys_avail, total_lowmem - PAGE_SIZE, PAGE_SIZE, 1); + + /* Determine number of entries necessary to cover lowmem */ + pinned_tlbs = (unsigned int) + (_ALIGN(total_lowmem, PPC44x_PIN_SIZE) >> PPC44x_PIN_SHIFT); + + /* Write upper watermark to save location */ + tlb_44x_hwater = PPC44x_LOW_SLOT - pinned_tlbs; + + /* If necessary, set additional pinned TLBs */ + if (pinned_tlbs > 1) + for (i = (PPC44x_LOW_SLOT-(pinned_tlbs-1)); i < PPC44x_LOW_SLOT; i++) { + unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC44x_PIN_SIZE; + ppc44x_pin_tlb(i, phys_addr+PAGE_OFFSET, phys_addr); + } + + /* Make sure vmalloc doesn't use virtual space covered by + the last pinned TLB entry. */ + vmalloc_start = KERNELBASE + _ALIGN(total_lowmem, PPC44x_PIN_SIZE); +} + +/* + * MMU_init_hw does the chip-specific initialization of the MMU hardware. + */ +void __init MMU_init_hw(void) +{ + flush_instruction_cache(); + + ppc44x_tlb_config(); +} diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/mm/4xx_mmu.c cset-v2.4.20/arch/ppc/mm/4xx_mmu.c --- cset-v2.4.20~/arch/ppc/mm/4xx_mmu.c 2004-10-25 14:58:33.000000000 +0900 +++ cset-v2.4.20/arch/ppc/mm/4xx_mmu.c 2004-11-01 22:35:09.000000000 +0900 @@ -54,11 +54,6 @@ #include #include -/* Used by the 4xx TLB replacement exception handler. - * Just needed it declared someplace (and initialized to zero). - */ -unsigned int tlb_4xx_index; - /* * MMU_init_hw does the chip-specific initialization of the MMU hardware. */ @@ -92,7 +87,14 @@ * Cache instruction and data space where the exception * vectors and the kernel live in real-mode. */ + /* + * Once the following code is enhanced to not assume that it should + * just enable caching on the first 512MB, we need to make sure that + * we either are given the cache in a known state or handle correctly + * the cache being enabled previously. Currently this will clear + * without flushing. -- Tom + */ - mtspr(SPRN_DCCR, 0x80000000); /* 128 MB of data space at 0x0. */ - mtspr(SPRN_ICCR, 0x80000000); /* 128 MB of instr. space at 0x0. */ + mtspr(SPRN_DCCR, 0xF0000000); /* 512 MB of data space at 0x0. */ + mtspr(SPRN_ICCR, 0xF0000000); /* 512 MB of instr. space at 0x0. */ } diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/mm/4xx_tlb.c cset-v2.4.20/arch/ppc/mm/4xx_tlb.c --- cset-v2.4.20~/arch/ppc/mm/4xx_tlb.c 2004-10-25 15:05:15.000000000 +0900 +++ cset-v2.4.20/arch/ppc/mm/4xx_tlb.c 2004-11-01 22:35:09.000000000 +0900 @@ -1,361 +1,3 @@ /* * BK Id: SCCS/s.4xx_tlb.c 1.5 05/17/01 18:14:23 cort */ -/* - * - * Copyright (c) 1998-1999 TiVo, Inc. - * Original implementation. - * Copyright (c) 1999-2000 Grant Erickson - * Minor rework. - * - * Module name: 4xx_tlb.c - * - * Description: - * Routines for manipulating the TLB on PowerPC 400-class processors. - * - */ - -#include - -#include -#include -#include -#include -#include - - -/* Preprocessor Defines */ - -#if !defined(TRUE) || TRUE != 1 -#define TRUE 1 -#endif - -#if !defined(FALSE) || FALSE != 0 -#define FALSE 0 -#endif - - -/* Global Variables */ - -static int pinned = 0; - - -/* Function Prototypes */ - -static int PPC4xx_tlb_miss(struct pt_regs *, unsigned long, int); - -extern void do_page_fault(struct pt_regs *, unsigned long, unsigned long); - - -/* - * () - * - * Description: - * This routine... - * - * Input(s): - * - * - * Output(s): - * - * - * Returns: - * - * - */ -static inline void -PPC4xx_tlb_write(unsigned long tag, unsigned long data, unsigned int index) -{ - asm("tlbwe %0,%1,1" : : "r" (data), "r" (index)); - asm("tlbwe %0,%1,0" : : "r" (tag), "r" (index)); -} - -/* - * () - * - * Description: - * This routine... - * - * Input(s): - * - * - * Output(s): - * - * - * Returns: - * - * - */ -void -PPC4xx_flush_tlb_all(void) -{ - int i; - unsigned long flags, pid; - - save_flags(flags); - cli(); - - pid = mfspr(SPRN_PID); - mtspr(SPRN_PID, 0); - - for (i = pinned; i < PPC4XX_TLB_SIZE; i++) { - PPC4xx_tlb_write(0, 0, i); - } - asm("sync;isync"); - - mtspr(SPRN_PID, pid); - restore_flags(flags); -} - -/* - * () - * - * Description: - * This routine... - * - * Input(s): - * - * - * Output(s): - * - * - * Returns: - * - * - */ -void -PPC4xx_dtlb_miss(struct pt_regs *regs) -{ - unsigned long addr = mfspr(SPRN_DEAR); - int write = mfspr(SPRN_ESR) & ESR_DST; - - if (PPC4xx_tlb_miss(regs, addr, write) < 0) { - sti(); - do_page_fault(regs, addr, write); - cli(); - } - -} - -/* - * () - * - * Description: - * This routine... - * - * Input(s): - * - * - * Output(s): - * - * - * Returns: - * - * - */ -void -PPC4xx_itlb_miss(struct pt_regs *regs) -{ - unsigned long addr = regs->nip; - - if (PPC4xx_tlb_miss(regs, addr, 0) < 0) { - sti(); - do_page_fault(regs, addr, 0); - cli(); - } -} - -/* - * () - * - * Description: - * This routine... - * - * Input(s): - * - * - * Output(s): - * - * - * Returns: - * - * - */ -void -PPC4xx_tlb_pin(unsigned long va, unsigned long pa, int pagesz, int cache) -{ - unsigned long tag, data; - unsigned long opid; - - if (pinned >= PPC4XX_TLB_SIZE) - return; - - opid = mfspr(SPRN_PID); - mtspr(SPRN_PID, 0); - - data = (pa & TLB_RPN_MASK) | TLB_WR; - - if (cache) - data |= (TLB_EX); - else - data |= (TLB_G | TLB_I); - - tag = (va & TLB_EPN_MASK) | TLB_VALID | pagesz; - - PPC4xx_tlb_write(tag, data, pinned++); - - mtspr(SPRN_PID, opid); - return; -} - -/* - * () - * - * Description: - * This routine... - * - * Input(s): - * - * - * Output(s): - * - * - * Returns: - * - * - */ -void -PPC4xx_tlb_unpin(unsigned long va, unsigned long pa, int size) -{ - /* XXX - To be implemented. */ -} - -/* - * () - * - * Description: - * This routine... - * - * Input(s): - * - * - * Output(s): - * - * - * Returns: - * - * - */ -static inline void -PPC4xx_tlb_update(unsigned long addr, pte_t *pte) -{ - unsigned long data, tag, rand; - int i, found = 1; - - /* Construct the hardware TLB entry from the Linux-style PTE */ - - tag = tag = (addr & PAGE_MASK) | TLB_VALID | TLB_PAGESZ(PAGESZ_4K); - data = data = (pte_val(*pte) & PAGE_MASK) | TLB_EX | TLB_WR; - -#if 0 - if (pte_val(*pte) & _PAGE_HWWRITE) - data |= TLB_WR; -#endif - - if (pte_val(*pte) & _PAGE_NO_CACHE) - data |= TLB_I; - - if (pte_val(*pte) & _PAGE_GUARDED) - data |= TLB_G; - - if (addr < KERNELBASE) - data |= TLB_ZSEL(1); - - /* Attempt to match the new tag to an existing entry in the TLB. */ - - asm("tlbsx. %0,0,%2;" - "beq 1f;" - "li %1,0;1:" : "=r" (i), "=r" (found) : "r" (tag)); - - /* - * If we found a match for the tag, reuse the entry index and update - * the tag and data portions. Otherwise, we did not find a match. Use - * the lower 5 bits of the lower time base register as a pseudo-random - * index into the TLB and replace the entry at that index. - */ - - if (found) { - PPC4xx_tlb_write(tag, data, i); - } else { - rand = mfspr(SPRN_TBLO) & (PPC4XX_TLB_SIZE - 1); - rand += pinned; - if (rand >= PPC4XX_TLB_SIZE) - rand -= pinned; - - PPC4xx_tlb_write(tag, data, rand); - asm("isync;sync"); - } -} - -/* - * () - * - * Description: - * This routine... - * - * Input(s): - * - * - * Output(s): - * - * - * Returns: - * - * - */ -static int -PPC4xx_tlb_miss(struct pt_regs *regs, unsigned long addr, int write) -{ - unsigned long spid, ospid; - struct mm_struct *mm; - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - if (!user_mode(regs) && (addr >= KERNELBASE)) { - mm = &init_mm; - spid = 0; - } else { - mm = current->mm; - spid = mfspr(SPRN_PID); - } - - pgd = pgd_offset(mm, addr); - if (pgd_none(*pgd)) - goto bad; - - pmd = pmd_offset(pgd, addr); - if (pmd_none(*pmd)) - goto bad; - - pte = pte_offset(pmd, addr); - if (pte_none(*pte) || !pte_present(*pte)) - goto bad; - - if (write) { - if (!pte_write(*pte)) - goto bad; - - set_pte(pte, pte_mkdirty(*pte)); - } - set_pte(pte, pte_mkyoung(*pte)); - - ospid = mfspr(SPRN_PID); - mtspr(SPRN_PID, spid); - PPC4xx_tlb_update(addr, pte); - mtspr(SPRN_PID, ospid); - - return (0); -bad: - return (-1); -} diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/mm/4xx_tlb.h cset-v2.4.20/arch/ppc/mm/4xx_tlb.h --- cset-v2.4.20~/arch/ppc/mm/4xx_tlb.h 2004-10-25 15:04:25.000000000 +0900 +++ cset-v2.4.20/arch/ppc/mm/4xx_tlb.h 2004-11-01 22:35:09.000000000 +0900 @@ -1,38 +1,3 @@ /* * BK Id: SCCS/s.4xx_tlb.h 1.5 05/17/01 18:14:23 cort */ -/* - * - * Copyright (c) 1999 Grant Erickson - * - * Module name: 4xx_tlb.h - * - * Description: - * Routines for manipulating the TLB on PowerPC 400-class processors. - * - */ - -#ifndef __4XX_TLB_H__ -#define __4XX_TLB_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - - -/* Function Prototypes */ - -extern void PPC4xx_tlb_pin(unsigned long va, unsigned long pa, - int pagesz, int cache); -extern void PPC4xx_tlb_unpin(unsigned long va, unsigned long pa, - int size); -extern void PPC4xx_tlb_flush_all(void); -extern void PPC4xx_tlb_flush(unsigned long va, int pid); - - -#ifdef __cplusplus -} -#endif - -#endif /* __4XX_TLB_H__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/mm/Makefile cset-v2.4.20/arch/ppc/mm/Makefile --- cset-v2.4.20~/arch/ppc/mm/Makefile 2004-10-25 15:01:43.000000000 +0900 +++ cset-v2.4.20/arch/ppc/mm/Makefile 2004-11-01 22:35:09.000000000 +0900 @@ -21,7 +21,8 @@ obj-$(CONFIG_PPC_STD_MMU) += hashtable.o ppc_mmu.o tlb.o obj-$(CONFIG_PPC_ISERIES) += iSeries_hashtable.o iSeries_mmu.o tlb.o -obj-$(CONFIG_4xx) += cachemap.o 4xx_mmu.o -obj-$(CONFIG_8xx) += cachemap.o +obj-$(CONFIG_40x) += 4xx_mmu.o +obj-$(CONFIG_44x) += 44x_mmu.o +obj-$(CONFIG_NOT_COHERENT_CACHE) += cachemap.o include $(TOPDIR)/Rules.make diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/mm/cachemap.c cset-v2.4.20/arch/ppc/mm/cachemap.c --- cset-v2.4.20~/arch/ppc/mm/cachemap.c 2004-10-25 15:04:17.000000000 +0900 +++ cset-v2.4.20/arch/ppc/mm/cachemap.c 2004-11-01 22:35:09.000000000 +0900 @@ -13,6 +13,7 @@ * is the virtual address and 'dma_handle' is the physical address. * Mostly stolen from the ARM port, with some changes for PowerPC. * -- Dan + * Modified for 36-bit support. -Matt * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -50,14 +51,24 @@ #include #include -extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep); +#include "mmu_decl.h" +extern int map_page(unsigned long va, phys_addr_t pa, int flags); + +/* This function will allocate the requested contiguous pages and + * map them into the kernel's vmalloc() space. This is done so we + * get unique mapping for these pages, outside of the kernel's 1:1 + * virtual:physical mapping. This is necessary so we can cover large + * portions of the kernel with single large page TLB entries, and + * still get unique uncached pages for consistent DMA. + */ void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle) { - int order, rsize; - unsigned long page; + int order, err, i; + unsigned long page, va, flags; + phys_addr_t pa; + struct vm_struct *area; void *ret; - pte_t *pte; if (in_interrupt()) BUG(); @@ -79,66 +90,54 @@ */ invalidate_dcache_range(page, page + size); - ret = (void *)page; - *dma_handle = virt_to_bus(ret); + /* Allocate some common virtual space to map the new pages. + */ + area = get_vm_area(size, VM_ALLOC); + if (area == 0) { + free_pages(page, order); + return NULL; + } + va = VMALLOC_VMADDR(area->addr); + ret = (void *)va; + + /* This gives us the real physical address of the first page. + */ + *dma_handle = pa = virt_to_bus((void *)page); + + flags = _PAGE_KERNEL | _PAGE_NO_CACHE; - /* Chase down all of the PTEs and mark them uncached. + /* + * Set refcount=1 on all pages in an order>0 + * allocation so that vfree() will actually + * free all pages that were allocated. */ - rsize = (int)size; - while (rsize > 0) { - if (get_pteptr(&init_mm, page, &pte)) { - pte_val(*pte) |= _PAGE_NO_CACHE | _PAGE_GUARDED; - flush_tlb_page(find_vma(&init_mm,page),page); + if (order > 0) + { + struct page *rpage = virt_to_page(page); + for (i = 1; i < (1 << order); i++) + set_page_count(rpage+i, 1); } - else { - BUG(); + + err = 0; + for (i = 0; i < size && err == 0; i += PAGE_SIZE) + err = map_page(va+i, pa+i, flags); + + if (err) { + vfree((void *)va); return NULL; } - page += PAGE_SIZE; - rsize -= PAGE_SIZE; - } return ret; } /* * free page(s) as defined by the above mapping. - * The caller has to tell us the size so we can free the proper number - * of pages. We can't vmalloc() a new space for these pages and simply - * call vfree() like some other architectures because we could end up - * with aliased cache lines (or at least a cache line with the wrong - * attributes). This can happen when the PowerPC speculative loads - * across page boundaries. */ -void consistent_free(void *vaddr, size_t size) +void consistent_free(void *vaddr) { - int order, rsize; - unsigned long addr; - pte_t *pte; - if (in_interrupt()) BUG(); - - size = PAGE_ALIGN(size); - order = get_order(size); - - /* Chase down all of the PTEs and mark them cached again. - */ - addr = (unsigned long)vaddr; - rsize = (int)size; - while (rsize > 0) { - if (get_pteptr(&init_mm, addr, &pte)) { - pte_val(*pte) &= ~(_PAGE_NO_CACHE | _PAGE_GUARDED); - flush_tlb_page(find_vma(&init_mm,addr),addr); - } - else { - BUG(); - return; - } - addr += PAGE_SIZE; - rsize -= PAGE_SIZE; - } - free_pages((unsigned long)vaddr, order); + vfree(vaddr); } /* @@ -163,3 +162,17 @@ break; } } + +/* + * consistent_sync_page make a page are consistent. identical + * to consistent_sync, but takes a struct page instead of a virtual address + */ + +void consistent_sync_page(struct page *page, unsigned long offset, +size_t size, int direction) +{ + void *start; + + start = page_address(page) + offset; + consistent_sync(start, size, direction); +} diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/mm/fault.c cset-v2.4.20/arch/ppc/mm/fault.c --- cset-v2.4.20~/arch/ppc/mm/fault.c 2004-10-25 15:02:04.000000000 +0900 +++ cset-v2.4.20/arch/ppc/mm/fault.c 2004-11-01 22:35:09.000000000 +0900 @@ -68,7 +68,7 @@ struct mm_struct *mm = current->mm; siginfo_t info; int code = SEGV_MAPERR; -#if defined(CONFIG_4xx) +#if defined(CONFIG_4xx) || defined (CONFIG_BOOKE) int is_write = error_code & ESR_DST; #else int is_write = 0; @@ -83,14 +83,14 @@ error_code &= 0x48200000; else is_write = error_code & 0x02000000; -#endif /* CONFIG_4xx */ +#endif /* CONFIG_4xx || CONFIG_BOOKE */ #if defined(CONFIG_XMON) || defined(CONFIG_KGDB) if (debugger_fault_handler && regs->trap == 0x300) { debugger_fault_handler(regs); return; } -#if !defined(CONFIG_4xx) +#ifndef CONFIG_4xx if (error_code & 0x00400000) { /* DABR match */ if (debugger_dabr_match(regs)) diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/mm/hashtable.S cset-v2.4.20/arch/ppc/mm/hashtable.S --- cset-v2.4.20~/arch/ppc/mm/hashtable.S 2004-10-25 15:02:07.000000000 +0900 +++ cset-v2.4.20/arch/ppc/mm/hashtable.S 2004-11-01 22:35:09.000000000 +0900 @@ -27,7 +27,6 @@ */ #include -#include #include #include #include @@ -335,25 +334,6 @@ ori r8,r8,_PAGE_COHERENT /* set M (coherence required) */ #endif -#ifdef CONFIG_POWER4 - /* - * XXX hack hack hack - translate 32-bit "physical" addresses - * in the linux page tables to 42-bit real addresses in such - * a fashion that we can get at the I/O we need to access. - * -- paulus - */ - cmpwi r8,0 - rlwinm r0,r8,16,16,30 - bge 57f - cmplwi r0,0xfe00 - li r0,0x3fd - bne 56f - li r0,0x3ff -56: sldi r0,r0,32 - or r8,r8,r0 -57: -#endif - /* Construct the high word of the PPC-style PTE (r5) */ #ifndef CONFIG_PPC64BRIDGE rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/mm/init.c cset-v2.4.20/arch/ppc/mm/init.c --- cset-v2.4.20~/arch/ppc/mm/init.c 2004-10-25 15:01:10.000000000 +0900 +++ cset-v2.4.20/arch/ppc/mm/init.c 2004-11-01 22:35:09.000000000 +0900 @@ -49,12 +49,39 @@ #include "mem_pieces.h" #include "mmu_decl.h" +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 64MB value just means that there will be a 64MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + * + * We no longer map larger than phys RAM with the BATs so we don't have + * to worry about the VMALLOC_OFFSET causing problems. We do have to worry + * about clashes between our early calls to ioremap() that start growing down + * from ioremap_base being run into the VM area allocations (growing upwards + * from VMALLOC_START). For this reason we have ioremap_bot to check when + * we actually run into our mappings setup in the early boot with the VM + * system. This really does become a problem for machines with good amounts + * of RAM. -- Cort + */ +#ifdef CONFIG_PIN_TLB +#define VMALLOC_OFFSET (0x2000000) /* 32M */ +#else +#define VMALLOC_OFFSET (0x1000000) /* 16M */ +#endif + +unsigned long vmalloc_start; + mmu_gather_t mmu_gathers[NR_CPUS]; -void *end_of_DRAM; unsigned long total_memory; unsigned long total_lowmem; +unsigned long ppc_memstart; +unsigned long ppc_memoffset = PAGE_OFFSET; + int mem_init_done; int init_bootmem_done; int boot_mapsize; @@ -313,8 +340,8 @@ total_memory = __max_memory; total_lowmem = total_memory; adjust_total_lowmem(); - end_of_DRAM = __va(total_lowmem); set_phys_avail(total_lowmem); + vmalloc_start = KERNELBASE + total_lowmem; /* Initialize the MMU hardware */ if (ppc_md.progress) @@ -396,8 +423,11 @@ } start = PAGE_ALIGN(start); - boot_mapsize = init_bootmem(start >> PAGE_SHIFT, - total_lowmem >> PAGE_SHIFT); + min_low_pfn = start >> PAGE_SHIFT; + max_low_pfn = (PPC_MEMSTART + total_lowmem) >> PAGE_SHIFT; + boot_mapsize = init_bootmem_node(&contig_page_data, min_low_pfn, + PPC_MEMSTART >> PAGE_SHIFT, + max_low_pfn); /* remove the bootmem bitmap from the available memory */ mem_pieces_remove(&phys_avail, start, boot_mapsize, 1); @@ -450,16 +480,17 @@ highmem_mapnr = total_lowmem >> PAGE_SHIFT; highmem_start_page = mem_map + highmem_mapnr; - max_mapnr = total_memory >> PAGE_SHIFT; -#else - max_mapnr = max_low_pfn; #endif /* CONFIG_HIGHMEM */ + max_mapnr = total_memory >> PAGE_SHIFT; - high_memory = (void *) __va(max_low_pfn * PAGE_SIZE); + high_memory = (void *) __va(PPC_MEMSTART + total_lowmem); num_physpages = max_mapnr; /* RAM is assumed contiguous */ totalram_pages += free_all_bootmem(); + /* adjust vmalloc_start */ + vmalloc_start = (vmalloc_start + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1); + #ifdef CONFIG_BLK_DEV_INITRD /* if we are booted from BootX with an initial ramdisk, make sure the ramdisk pages aren't reserved. */ @@ -485,7 +516,7 @@ addr += PAGE_SIZE) SetPageReserved(virt_to_page(addr)); - for (addr = PAGE_OFFSET; addr < (unsigned long)end_of_DRAM; + for (addr = PAGE_OFFSET; addr < (unsigned long)high_memory; addr += PAGE_SIZE) { if (!PageReserved(virt_to_page(addr))) continue; @@ -544,7 +575,7 @@ * physical memory. */ - phys_avail.regions[0].address = 0; + phys_avail.regions[0].address = PPC_MEMSTART; phys_avail.regions[0].size = total_memory; phys_avail.n_regions = 1; diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/mm/mmu_decl.h cset-v2.4.20/arch/ppc/mm/mmu_decl.h --- cset-v2.4.20~/arch/ppc/mm/mmu_decl.h 2004-10-25 15:04:54.000000000 +0900 +++ cset-v2.4.20/arch/ppc/mm/mmu_decl.h 2004-11-02 17:54:31.000000000 +0900 @@ -24,24 +24,23 @@ */ #include +#include extern void mapin_ram(void); extern void bat_mapin_ram(unsigned long bat2, unsigned long bat3); extern void adjust_total_lowmem(void); -extern int map_page(unsigned long va, unsigned long pa, int flags); +extern int map_page(unsigned long va, phys_addr_t pa, int flags); extern void setbat(int index, unsigned long virt, unsigned long phys, unsigned int size, int flags); extern void reserve_phys_mem(unsigned long start, unsigned long size); extern int __map_without_bats; -extern void *end_of_DRAM; extern unsigned long ioremap_base; extern unsigned long ioremap_bot; extern unsigned int rtas_data, rtas_size; extern unsigned long total_memory; extern unsigned long total_lowmem; -extern unsigned long ram_phys_base; extern int mem_init_done; extern PTE *Hash, *Hash_end; diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/mm/pgtable.c cset-v2.4.20/arch/ppc/mm/pgtable.c --- cset-v2.4.20~/arch/ppc/mm/pgtable.c 2004-10-25 15:00:52.000000000 +0900 +++ cset-v2.4.20/arch/ppc/mm/pgtable.c 2004-11-01 22:35:09.000000000 +0900 @@ -32,11 +32,10 @@ #include #include #include +#include #include "mmu_decl.h" -unsigned long ram_phys_base; - unsigned long ioremap_base; unsigned long ioremap_bot; int io_bat_index; @@ -71,17 +70,35 @@ #define p_mapped_by_bats(x) (0UL) #endif /* HAVE_BATS */ -#ifndef CONFIG_PPC_ISERIES +#ifdef CONFIG_44x +void * +ioremap(phys_addr_t addr, unsigned long size) +{ + phys_addr_t addr64 = fixup_bigphys_addr(addr, size);; + + return ioremap64(addr64, size); +} + +void * +ioremap64(unsigned long long addr, unsigned long size) +{ + return __ioremap(addr, size, _PAGE_NO_CACHE); +} + +#else /* CONFIG_44x */ + void * -ioremap(unsigned long addr, unsigned long size) +ioremap(phys_addr_t addr, unsigned long size) { return __ioremap(addr, size, _PAGE_NO_CACHE); } +#endif /* CONFIG_44x */ void * -__ioremap(unsigned long addr, unsigned long size, unsigned long flags) +__ioremap(phys_addr_t addr, unsigned long size, unsigned long flags) { - unsigned long p, v, i; + unsigned long v, i; + phys_addr_t p; int err; /* @@ -106,7 +123,7 @@ */ if ( mem_init_done && (p < virt_to_phys(high_memory)) ) { - printk("__ioremap(): phys addr %0lx is RAM lr %p\n", p, + printk("__ioremap(): phys addr "PTE_FMT" is RAM lr %p\n", p, __builtin_return_address(0)); return NULL; } @@ -157,7 +174,7 @@ } out: - return (void *) (v + (addr & ~PAGE_MASK)); + return (void *) (v + ((unsigned long)addr & ~PAGE_MASK)); } void iounmap(void *addr) @@ -171,10 +188,9 @@ if (addr > high_memory && (unsigned long) addr < ioremap_bot) vfree((void *) (PAGE_MASK & (unsigned long) addr)); } -#endif /* CONFIG_PPC_ISERIES */ int -map_page(unsigned long va, unsigned long pa, int flags) +map_page(unsigned long va, phys_addr_t pa, int flags) { pmd_t *pd; pte_t *pg; @@ -203,7 +219,7 @@ #ifdef HAVE_BATS unsigned long bat_max = 0x10000000; unsigned long align; - unsigned long ram = total_lowmem; + unsigned long ram; int is601 = 0; /* 601s have smaller BATs */ @@ -212,10 +228,20 @@ is601 = 1; } + /* adjust BAT block size to max_low_mem */ + if (max_low_mem < bat_max) + bat_max = max_low_mem; + + /* adjust lowmem size to max_low_mem */ + if (max_low_mem < total_lowmem) + ram = max_low_mem; + else + ram = total_lowmem; + /* Make sure we don't map a block larger than the smallest alignment of the physical address. */ - /* alignment of ram_phys_base */ - align = ~(ram_phys_base-1) & ram_phys_base; + /* alignment of PPC_MEMSTART */ + align = ~(PPC_MEMSTART-1) & PPC_MEMSTART; /* set BAT block size to MIN(max_size, align) */ if (align && align < bat_max) bat_max = align; @@ -232,8 +258,9 @@ ram -= __bat3; } - printk(KERN_INFO "Memory BAT mapping: BAT2=%ldMb, BAT3=%ldMb, residual: %ldMb\n", - __bat2 >> 20, __bat3 >> 20, ram >> 20); + printk(KERN_INFO "Memory BAT mapping: BAT2=%ldMb, BAT3=%ldMb," + " residual: %ldMb\n", __bat2 >> 20, __bat3 >> 20, + (total_lowmem - (__bat2 - __bat3)) >> 20); /* On SMP, we limit the lowmem to the area mapped with BATs. * We also assume nobody will do SMP with 601s @@ -247,8 +274,9 @@ if (total_lowmem > max_low_mem) { total_lowmem = max_low_mem; #ifndef CONFIG_HIGHMEM - printk(KERN_INFO "Warning, memory limited to %ld Mb, use CONFIG_HIGHMEM" - " to reach %ld Mb\n", max_low_mem >> 20, total_lowmem >> 20); + printk(KERN_INFO "Warning, memory limited to %ld Mb, use " + "CONFIG_HIGHMEM to reach %ld Mb\n", + max_low_mem >> 20, total_memory >> 20); total_memory = total_lowmem; #endif /* CONFIG_HIGHMEM */ } @@ -267,16 +295,16 @@ #endif /* HAVE_BATS */ v = KERNELBASE; - p = ram_phys_base; + p = PPC_MEMSTART; for (s = 0; s < total_lowmem; s += PAGE_SIZE) { /* On the MPC8xx, we want the page shared so we * don't get ASID compares on kernel space. */ - f = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_SHARED; -#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) + f = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_SHARED | _PAGE_HWEXEC; +#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) /* Allows stub to set breakpoints everywhere */ f |= _PAGE_WRENABLE; -#else /* !CONFIG_KGDB && !CONFIG_XMON */ +#else /* !CONFIG_KGDB && !CONFIG_XMON && !CONFIG_BDI_SWITCH */ if ((char *) v < _stext || (char *) v >= etext) f |= _PAGE_WRENABLE; #ifdef CONFIG_PPC_STD_MMU @@ -290,6 +318,8 @@ v += PAGE_SIZE; p += PAGE_SIZE; } + if (ppc_md.progress) + ppc_md.progress("MMU:mapin_ram done", 0x401); } /* is x a power of 2? */ @@ -300,7 +330,7 @@ * virt, phys, size must all be page-aligned. * This should only be called before ioremap is called. */ -void __init io_block_mapping(unsigned long virt, unsigned long phys, +void __init io_block_mapping(unsigned long virt, phys_addr_t phys, unsigned int size, int flags) { int i; diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/mm/ppc_mmu.c cset-v2.4.20/arch/ppc/mm/ppc_mmu.c --- cset-v2.4.20~/arch/ppc/mm/ppc_mmu.c 2004-10-25 15:00:15.000000000 +0900 +++ cset-v2.4.20/arch/ppc/mm/ppc_mmu.c 2004-11-01 22:35:09.000000000 +0900 @@ -91,11 +91,11 @@ unsigned long tot, done; tot = total_lowmem; - setbat(2, KERNELBASE, ram_phys_base, bat2, _PAGE_KERNEL); + setbat(2, KERNELBASE, PPC_MEMSTART, bat2, _PAGE_KERNEL); done = (unsigned long)bat_addrs[2].limit - KERNELBASE + 1; if ((done < tot) && !bat_addrs[3].limit && bat3) { tot -= done; - setbat(3, KERNELBASE+done, ram_phys_base+done, bat3, + setbat(3, KERNELBASE+done, PPC_MEMSTART+done, bat3, _PAGE_KERNEL); } } diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/platforms/Makefile cset-v2.4.20/arch/ppc/platforms/Makefile --- cset-v2.4.20~/arch/ppc/platforms/Makefile 2004-10-25 15:04:49.000000000 +0900 +++ cset-v2.4.20/arch/ppc/platforms/Makefile 2004-11-01 22:35:09.000000000 +0900 @@ -28,8 +28,14 @@ O_TARGET := platform.o -export-objs := prep_setup.o +export-objs := prep_setup.o ibm440gp.o ibm440gx.o +obj-$(CONFIG_405GP) += ibm405gp.o +obj-$(CONFIG_440GP) += ibm440gp.o +obj-$(CONFIG_440GX) += ibm440gx.o + +obj-$(CONFIG_EBONY) += ebony.o +obj-$(CONFIG_OCOTEA) += ocotea.o obj-$(CONFIG_WALNUT) += walnut.o obj-$(CONFIG_APUS) += apus_setup.o diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/platforms/ebony.c cset-v2.4.20/arch/ppc/platforms/ebony.c --- cset-v2.4.20~/arch/ppc/platforms/ebony.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/platforms/ebony.c 2004-11-02 17:38:17.000000000 +0900 @@ -0,0 +1,534 @@ +/* + * arch/ppc/platforms/ebony.c + * + * Ebony board specific routines + * + * Matt Porter + * + * Copyright 2002-2003 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +extern void abort(void); +extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode); +extern int pckbd_getkeycode(unsigned int scancode); +extern int pckbd_translate(unsigned char scancode, unsigned char *keycode, + char raw_mode); +extern void gen550_progress(char *, unsigned short); +extern void gen550_init(int, struct serial_struct *); + +/* + * Ebony IRQ triggering/polarity settings + */ +static u_char ebony_IRQ_initsenses[] __initdata = { + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 0: UART 0 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 1: UART 1 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 2: IIC 0 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 3: IIC 1 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 4: PCI Inb Mess */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 5: PCI Cmd Wrt */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 6: PCI PM */ + (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 7: PCI MSI 0 */ + (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 8: PCI MSI 1 */ + (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 9: PCI MSI 2 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 10: MAL TX EOB */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 11: MAL RX EOB */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 12: DMA Chan 0 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 13: DMA Chan 1 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 14: DMA Chan 2 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 15: DMA Chan 3 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 16: Reserved */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 17: Reserved */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 18: GPT Timer 0 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 19: GPT Timer 1 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 20: GPT Timer 2 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 21: GPT Timer 3 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 22: GPT Timer 4 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 23: Ext Int 0 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 24: Ext Int 1 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 25: Ext Int 2 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 26: Ext Int 3 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 27: Ext Int 4 */ + (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* 28: Ext Int 5 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 29: Ext Int 6 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 30: UIC1 NC Int */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 31: UIC1 Crit Int */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 32: MAL SERR */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 33: MAL TXDE */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 34: MAL RXDE */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 35: ECC Unc Err */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 36: ECC Corr Err */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 37: Ext Bus Ctrl */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 38: Ext Bus Mstr */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 39: OPB->PLB */ + (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 40: PCI MSI 3 */ + (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 41: PCI MSI 4 */ + (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 42: PCI MSI 5 */ + (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 43: PCI MSI 6 */ + (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 44: PCI MSI 7 */ + (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 45: PCI MSI 8 */ + (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 46: PCI MSI 9 */ + (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 47: PCI MSI 10 */ + (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 48: PCI MSI 11 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 49: PLB Perf Mon */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 50: Ext Int 7 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 51: Ext Int 8 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 52: Ext Int 9 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 53: Ext Int 10 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 54: Ext Int 11 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 55: Ext Int 12 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 56: Ser ROM Err */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 57: Reserved */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 58: Reserved */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 59: PCI Async Err */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 60: EMAC 0 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 61: EMAC 0 WOL */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 62: EMAC 1 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 63: EMAC 1 WOL */ +}; + +/* Global Variables */ +unsigned char __res[sizeof (bd_t)]; + +static void __init +ebony_calibrate_decr(void) +{ + unsigned int freq; + + /* + * Determine system clock speed + * + * If we are on Rev. B silicon, then use + * default external system clock. If we are + * on Rev. C silicon then errata forces us to + * use the internal clock. + */ + switch (PVR_REV(mfspr(PVR))) { + case PVR_REV(PVR_440GP_RB): + freq = EBONY_440GP_RB_SYSCLK; + break; + case PVR_REV(PVR_440GP_RC1): + default: + freq = EBONY_440GP_RC_SYSCLK; + break; + } + + tb_ticks_per_jiffy = freq / HZ; + tb_to_us = mulhwu_scale_factor(freq, 1000000); + + /* Set the time base to zero */ + mtspr(SPRN_TBWL, 0); + mtspr(SPRN_TBWU, 0); + + /* Clear any pending timer interrupts */ + mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS); + + /* Enable decrementer interrupt */ + mtspr(SPRN_TCR, TCR_DIE); +} + +static int +ebony_show_cpuinfo(struct seq_file *m) +{ + seq_printf(m, "vendor\t\t: IBM\n"); + seq_printf(m, "machine\t\t: Ebony\n"); + + return 0; +} + +static inline int +ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) +{ + static char pci_irq_table[][4] = + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + { + { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */ + { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */ + { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */ + { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */ + }; + + const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; + return PCI_IRQ_TABLE_LOOKUP; +} + +#define PCIX_READW(offset) \ + (readw((u32)pcix_reg_base+offset)) + +#define PCIX_WRITEW(value, offset) \ + (writew(value, (u32)pcix_reg_base+offset)) + +#define PCIX_WRITEL(value, offset) \ + (writel(value, (u32)pcix_reg_base+offset)) + +/* + * FIXME: This is only here to "make it work". This will move + * to a ibm_pcix.c which will contain a generic IBM PCIX bridge + * configuration library. -Matt + */ +static void __init +ebony_setup_pcix(void) +{ + void *pcix_reg_base; + + pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX0_REG_SIZE); + + /* Enable PCIX0 I/O, Mem, and Busmaster cycles */ + PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND); + + /* Disable all windows */ + PCIX_WRITEL(0, PCIX0_POM0SA); + PCIX_WRITEL(0, PCIX0_POM1SA); + PCIX_WRITEL(0, PCIX0_POM2SA); + PCIX_WRITEL(0, PCIX0_PIM0SA); + PCIX_WRITEL(0, PCIX0_PIM1SA); + PCIX_WRITEL(0, PCIX0_PIM2SA); + + /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */ + PCIX_WRITEL(0x00000003, PCIX0_POM0LAH); + PCIX_WRITEL(0x80000000, PCIX0_POM0LAL); + PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH); + PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL); + PCIX_WRITEL(0x80000001, PCIX0_POM0SA); + + /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ + PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); + PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); + PCIX_WRITEL(0x80000007, PCIX0_PIM0SA); + + eieio(); +} + +static void __init +ebony_setup_hose(void) +{ + struct pci_controller *hose; + + /* Configure windows on the PCI-X host bridge */ + ebony_setup_pcix(); + + hose = pcibios_alloc_controller(); + + if (!hose) + return; + + hose->first_busno = 0; + hose->last_busno = 0xff; + + hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET; + + pci_init_resource(&hose->io_resource, + EBONY_PCI_LOWER_IO, + EBONY_PCI_UPPER_IO, + IORESOURCE_IO, + "PCI host bridge"); + + pci_init_resource(&hose->mem_resources[0], + EBONY_PCI_LOWER_MEM, + EBONY_PCI_UPPER_MEM, + IORESOURCE_MEM, + "PCI host bridge"); + + hose->io_space.start = EBONY_PCI_LOWER_IO; + hose->io_space.end = EBONY_PCI_UPPER_IO; + hose->mem_space.start = EBONY_PCI_LOWER_MEM; + hose->mem_space.end = EBONY_PCI_UPPER_MEM; + isa_io_base = + (unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE); + hose->io_base_virt = (void *)isa_io_base; + + setup_indirect_pci(hose, + EBONY_PCI_CFGA_PLB32, + EBONY_PCI_CFGD_PLB32); + hose->set_cfg_type = 1; + + hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); + + ppc_md.pci_swizzle = common_swizzle; + ppc_md.pci_map_irq = ebony_map_irq; +} + +TODC_ALLOC(); + +static void __init +ebony_early_serial_map(void) +{ + struct serial_struct serial_req; + + /* Setup ioremapped serial port access */ + memset(&serial_req, 0, sizeof(serial_req)); + serial_req.line = 0; + serial_req.baud_base = BASE_BAUD; + serial_req.port = 0; + serial_req.irq = 0; + serial_req.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; + serial_req.io_type = SERIAL_IO_MEM; + serial_req.iomem_base = ioremap64(PPC440GP_UART0_ADDR, 8); + serial_req.iomem_reg_shift = 0; + +#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) + /* Configure debug serial access */ + gen550_init(0, &serial_req); +#endif + + if (early_serial_setup(&serial_req) != 0) { + printk("Early serial init of port 0 failed\n"); + } + + /* Assume early_serial_setup() doesn't modify serial_req */ + serial_req.line = 1; + serial_req.port = 1; + serial_req.irq = 1; + serial_req.iomem_base = ioremap64(PPC440GP_UART1_ADDR, 8); + +#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) + /* Configure debug serial access */ + gen550_init(1, &serial_req); +#endif + + if (early_serial_setup(&serial_req) != 0) { + printk("Early serial init of port 1 failed\n"); + } +} + +static void __init +ebony_setup_arch(void) +{ + unsigned char * vpd_base; + struct ibm44x_clocks clocks; + bd_t *bip = (bd_t *) __res; + +#if !defined(CONFIG_BDI_SWITCH) + /* + * The Abatron BDI JTAG debugger does not tolerate others + * mucking with the debug registers. + */ + mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM)); +#endif + + /* Retrieve MAC addresses */ + vpd_base = ioremap64(EBONY_VPD_BASE, EBONY_VPD_SIZE); + memcpy(bip->bi_enetaddr[0],EBONY_NA0_ADDR(vpd_base),6); + memcpy(bip->bi_enetaddr[1],EBONY_NA1_ADDR(vpd_base),6); + + /* + * Determine various clocks. + * To be completely correct we should get SysClk + * from FPGA, because it can be changed by on-board switches + * --ebs + */ + ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200); + bip->bi_opb_busfreq = clocks.opb; + + /* Use IIC in standard (100 kHz) mode */ + bip->bi_iic_fast[0] = bip->bi_iic_fast[1] = 0; + + /* Setup TODC access */ + TODC_INIT(TODC_TYPE_DS1743, + 0, + 0, + ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE), + 8); + + /* init to some ~sane value until calibrate_delay() runs */ + loops_per_jiffy = 50000000/HZ; + + /* Setup PCI host bridge */ + ebony_setup_hose(); + +#ifdef CONFIG_BLK_DEV_INITRD + if (initrd_start) + ROOT_DEV = to_kdev_t(0x0100); /* /dev/ram */ + else +#endif +#ifdef CONFIG_ROOT_NFS + ROOT_DEV = to_kdev_t(0x00ff); /* /dev/nfs */ +#else + ROOT_DEV = to_kdev_t(0x0301); /* /dev/hda1 */ +#endif + +#ifdef CONFIG_VT + conswitchp = &dummy_con; +#endif + + ebony_early_serial_map(); + + ibm4xxPIC_InitSenses = ebony_IRQ_initsenses; + ibm4xxPIC_NumInitSenses = sizeof(ebony_IRQ_initsenses); + + /* Identify the system */ + printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n"); +} + +static void +ebony_restart(char *cmd) +{ + local_irq_disable(); + abort(); +} + +static void +ebony_power_off(void) +{ + local_irq_disable(); + for(;;); +} + +static void +ebony_halt(void) +{ + local_irq_disable(); + for(;;); +} + +/* + * Read the 440GP memory controller to get size of system memory. + */ +static unsigned long __init +ebony_find_end_of_memory(void) +{ + u32 i, bank_config; + u32 mem_size = 0; + + for (i=0; i<4; i++) + { + switch (i) + { + case 0: + mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR); + break; + case 1: + mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR); + break; + case 2: + mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR); + break; + case 3: + mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR); + break; + } + + bank_config = mfdcr(DCRN_SDRAM0_CFGDATA); + + if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE)) + continue; + switch (SDRAM_CONFIG_BANK_SIZE(bank_config)) + { + case SDRAM_CONFIG_SIZE_8M: + mem_size += PPC44x_MEM_SIZE_8M; + break; + case SDRAM_CONFIG_SIZE_16M: + mem_size += PPC44x_MEM_SIZE_16M; + break; + case SDRAM_CONFIG_SIZE_32M: + mem_size += PPC44x_MEM_SIZE_32M; + break; + case SDRAM_CONFIG_SIZE_64M: + mem_size += PPC44x_MEM_SIZE_64M; + break; + case SDRAM_CONFIG_SIZE_128M: + mem_size += PPC44x_MEM_SIZE_128M; + break; + case SDRAM_CONFIG_SIZE_256M: + mem_size += PPC44x_MEM_SIZE_256M; + break; + case SDRAM_CONFIG_SIZE_512M: + mem_size += PPC44x_MEM_SIZE_512M; + break; + } + } + return mem_size; +} + +static void __init +ebony_init_irq(void) +{ + int i; + + ppc4xx_pic_init(); + + for (i = 0; i < NR_IRQS; i++) + irq_desc[i].handler = ppc4xx_pic; +} + +void __init +platform_init(unsigned long r3, unsigned long r4, + unsigned long r5, unsigned long r6, unsigned long r7) +{ + parse_bootinfo(find_bootinfo()); + + ppc_md.setup_arch = ebony_setup_arch; + ppc_md.show_cpuinfo = ebony_show_cpuinfo; + ppc_md.init_IRQ = ebony_init_irq; + ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ + + ppc_md.find_end_of_memory = ebony_find_end_of_memory; + + ppc_md.restart = ebony_restart; + ppc_md.power_off = ebony_power_off; + ppc_md.halt = ebony_halt; + + ppc_md.calibrate_decr = ebony_calibrate_decr; + ppc_md.time_init = todc_time_init; + ppc_md.set_rtc_time = todc_set_rtc_time; + ppc_md.get_rtc_time = todc_get_rtc_time; + + ppc_md.nvram_read_val = todc_direct_read_val; + ppc_md.nvram_write_val = todc_direct_write_val; +#if defined(CONFIG_VT) + ppc_md.kbd_setkeycode = pckbd_setkeycode; + ppc_md.kbd_getkeycode = pckbd_getkeycode; + ppc_md.kbd_translate = pckbd_translate; + ppc_md.kbd_unexpected_up = pckbd_unexpected_up; + ppc_md.kbd_leds = pckbd_leds; + ppc_md.kbd_init_hw = 0; +#endif + +#ifdef CONFIG_SERIAL_TEXT_DEBUG + ppc_md.progress = gen550_progress; +#endif /* CONFIG_SERIAL_TEXT_DEBUG */ +#ifdef CONFIG_KGDB + ppc_md.early_serial_map = ebony_early_serial_map; +#endif +} + diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/platforms/ebony.h cset-v2.4.20/arch/ppc/platforms/ebony.h --- cset-v2.4.20~/arch/ppc/platforms/ebony.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/platforms/ebony.h 2004-11-01 22:35:09.000000000 +0900 @@ -0,0 +1,94 @@ +/* + * arch/ppc/platforms/ebony.h + * + * Ebony board definitions + * + * Matt Porter + * + * Copyright 2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifdef __KERNEL__ +#ifndef __ASM_EBONY_H__ +#define __ASM_EBONY_H__ + +#include +#include + +/* F/W TLB mapping used in bootloader glue to reset EMAC */ +#define PPC44x_EMAC0_MR0 0xE0000800 + +/* Macros to get at Ebony VPD info */ +#define EBONY_VPD_BASE 0x00000001fffffe00ULL +#define EBONY_VPD_SIZE 0x24 +#define EBONY_NA0_OFFSET 0x0c +#define EBONY_NA1_OFFSET 0x18 +#define EBONY_NA0_ADDR(base) (base + EBONY_NA0_OFFSET) +#define EBONY_NA1_ADDR(base) (base + EBONY_NA1_OFFSET) + +/* Default clock rates for Rev. B and Rev. C silicon */ +#define EBONY_440GP_RB_SYSCLK 33000000 +#define EBONY_440GP_RC_SYSCLK 400000000 + +/* RTC/NVRAM location */ +#define EBONY_RTC_ADDR 0x0000000148000000ULL +#define EBONY_RTC_SIZE 0x2000 + +/* Flash */ +#define EBONY_FPGA_ADDR 0x0000000148300000 +#define EBONY_BOOT_SMALL_FLASH(x) (x & 0x20) +#define EBONY_ONBRD_FLASH_EN(x) (x & 0x02) +#define EBONY_FLASH_SEL(x) (x & 0x01) +#define EBONY_SMALL_FLASH_LOW1 0x00000001ff800000 +#define EBONY_SMALL_FLASH_LOW2 0x00000001ff880000 +#define EBONY_SMALL_FLASH_HIGH1 0x00000001fff00000 +#define EBONY_SMALL_FLASH_HIGH2 0x00000001fff80000 +#define EBONY_SMALL_FLASH_SIZE 0x80000 +#define EBONY_LARGE_FLASH_LOW 0x00000001ff800000 +#define EBONY_LARGE_FLASH_HIGH 0x00000001ffc00000 +#define EBONY_LARGE_FLASH_SIZE 0x400000 + +#define EBONY_SMALL_FLASH_BASE 0x00000001fff80000 +#define EBONY_LARGE_FLASH_BASE 0x00000001ff800000 + +/* + * Serial port defines + */ + +/* OpenBIOS defined UART mappings, used before early_serial_setup */ +#define UART0_IO_BASE (u8 *) 0xE0000200 +#define UART1_IO_BASE (u8 *) 0xE0000300 + +#define BASE_BAUD 33000000/3/16 + +#define STD_UART_OP(num) \ + { 0, BASE_BAUD, 0, UART##num##_INT, \ + (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ + iomem_base: UART##num##_IO_BASE, \ + io_type: SERIAL_IO_MEM}, + +#define SERIAL_PORT_DFNS \ + STD_UART_OP(0) \ + STD_UART_OP(1) + +/* PCI support */ +#define EBONY_PCI_LOWER_IO 0x00000000 +#define EBONY_PCI_UPPER_IO 0x0000ffff +#define EBONY_PCI_LOWER_MEM 0x80002000 +#define EBONY_PCI_UPPER_MEM 0xffffefff + +#define EBONY_PCI_CFGREGS_BASE 0x000000020ec00000 +#define EBONY_PCI_CFGA_PLB32 0x0ec00000 +#define EBONY_PCI_CFGD_PLB32 0x0ec00004 + +#define EBONY_PCI_IO_BASE 0x0000000208000000ULL +#define EBONY_PCI_IO_SIZE 0x00010000 +#define EBONY_PCI_MEM_OFFSET 0x00000000 + +#endif /* __ASM_EBONY_H__ */ +#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/platforms/ibm405.h cset-v2.4.20/arch/ppc/platforms/ibm405.h --- cset-v2.4.20~/arch/ppc/platforms/ibm405.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/platforms/ibm405.h 2004-11-01 22:35:09.000000000 +0900 @@ -0,0 +1,332 @@ +/* + * ibm405.h + * + * This was derived from the ppc4xx.h and contains + * common 405 offsets + * + * Armin Kuster akuster@pacbell.net + * Jan, 2002 + * + * + * Copyright 2002 MontaVista Softare Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Version 1.0 (02/01/17) - A. Kuster + * Initial version - moved 405 specific out of the other core.h's + * + * Version 1.0 (02/08/02) - A. Kuster + * removed DCRN_UIC1_BASE to NP405L & H + * + * Version 1.2 (05/29/02) - Akuster + * removed DCRN_MALRXCTP2R etc, alread in ibmnp405.h + */ + +#ifdef __KERNEL__ +#ifndef __ASM_IBM405_H__ +#define __ASM_IBM405_H__ + +#ifdef DCRN_BE_BASE +#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */ +#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */ +#endif +/* DCRN_BESR */ +#define BESR_DSES 0x80000000 /* Data-Side Error Status */ +#define BESR_DMES 0x40000000 /* DMA Error Status */ +#define BESR_RWS 0x20000000 /* Read/Write Status */ +#define BESR_ETMASK 0x1C000000 /* Error Type */ +#define ET_PROT 0 +#define ET_PARITY 1 +#define ET_NCFG 2 +#define ET_BUSERR 4 +#define ET_BUSTO 6 + +/* Clock and power management shifts for emacs */ +#define IBM_CPM_EMMII 0 /* Shift value for MII */ +#define IBM_CPM_EMRX 1 /* Shift value for recv */ +#define IBM_CPM_EMTX 2 /* Shift value for MAC */ + +#ifdef DCRN_CHCR_BASE +#define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */ +#define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */ +#endif +#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */ + +#ifdef DCRN_CHPSR_BASE +#define DCRN_CHPSR (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */ +#endif + +#ifdef DCRN_CPMFR_BASE +#define DCRN_CPMFR (DCRN_CPMFR_BASE + 0x0) /* CPM Force */ +#endif + +#ifdef DCRN_CPMSR_BASE +#define DCRN_CPMSR (DCRN_CPMSR_BASE + 0x0) /* CPM Status */ +#define DCRN_CPMER (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */ +#endif + +#ifdef DCRN_DCP0_BASE +/* Decompression Controller Address */ +#define DCRN_DCP0_CFGADDR (DCRN_DCP0_BASE + 0x0) +/* Decompression Controller Data */ +#define DCRN_DCP0_CFGDATA (DCRN_DCP0_BASE + 0x1) +#else +#define DCRN_DCP0_CFGADDR 0x0 +#define DCRN_DCP0_CFGDATA 0x0 +#endif + +#ifdef DCRN_DMA0_BASE +/* DMA Channel Control Register 0 */ +#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) +#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */ +/* DMA Destination Address Register 0 */ +#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2) +/* DMA Source Address Register 0 */ +#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) +#ifdef DCRNCAP_DMA_CC +/* DMA Chained Count Register 0 */ +#define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4) +#endif +#ifdef DCRNCAP_DMA_SG +/* DMA Scatter/Gather Descriptor Addr 0 */ +#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4) +#endif +#endif + +#ifdef DCRN_DMA1_BASE +/* DMA Channel Control Register 1 */ +#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) +#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count Register 1 */ +/* DMA Destination Address Register 1 */ +#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x2) +/* DMA Source Address Register 1 */ +#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Source Address Register 1 */ +#ifdef DCRNCAP_DMA_CC +/* DMA Chained Count Register 1 */ +#define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4) +#endif +#ifdef DCRNCAP_DMA_SG +/* DMA Scatter/Gather Descriptor Addr 1 */ +#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4) +#endif +#endif + +#ifdef DCRN_DMA2_BASE +#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */ +#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */ +#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */ +#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */ +#ifdef DCRNCAP_DMA_CC +#define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */ +#endif +#ifdef DCRNCAP_DMA_SG +#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */ +#endif +#endif + +#ifdef DCRN_DMA3_BASE +#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */ +#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */ +#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */ +#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */ +#ifdef DCRNCAP_DMA_CC +#define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */ +#endif +#ifdef DCRNCAP_DMA_SG +#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */ +#endif +#endif + +#ifdef DCRN_DMASR_BASE +#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ +#ifdef DCRNCAP_DMA_SG +#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ +/* don't know if these two registers always exist if scatter/gather exists */ +#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ +#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ +#endif +#endif + +#ifdef DCRN_EBC_BASE +#define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */ +#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */ +#endif + +#ifdef DCRN_EXIER_BASE +#define DCRN_EXIER (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */ +#endif + +#ifdef DCRN_EXISR_BASE +#define DCRN_EXISR (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */ +#endif + +#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ +#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ +#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ +#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ +#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ +#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ +#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ +#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ +#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ +#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ +#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ +#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ +#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ +#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ + +#ifdef DCRN_IOCR_BASE +#define DCRN_IOCR (DCRN_IOCR_BASE + 0x0) /* Input/Output Configuration Register */ +#endif +#define IOCR_E0TE 0x80000000 +#define IOCR_E0LP 0x40000000 +#define IOCR_E1TE 0x20000000 +#define IOCR_E1LP 0x10000000 +#define IOCR_E2TE 0x08000000 +#define IOCR_E2LP 0x04000000 +#define IOCR_E3TE 0x02000000 +#define IOCR_E3LP 0x01000000 +#define IOCR_E4TE 0x00800000 +#define IOCR_E4LP 0x00400000 +#define IOCR_EDT 0x00080000 +#define IOCR_SOR 0x00040000 +#define IOCR_EDO 0x00008000 +#define IOCR_2XC 0x00004000 +#define IOCR_ATC 0x00002000 +#define IOCR_SPD 0x00001000 +#define IOCR_BEM 0x00000800 +#define IOCR_PTD 0x00000400 +#define IOCR_ARE 0x00000080 +#define IOCR_DRC 0x00000020 +#define IOCR_RDM(x) (((x) & 0x3) << 3) +#define IOCR_TCS 0x00000004 +#define IOCR_SCS 0x00000002 +#define IOCR_SPC 0x00000001 + +#define DCRN_MALCR(base) (base + 0x0) /* MAL Configuration */ +#define DCRN_MALDBR(base) ((base) + 0x3) /* Debug Register */ +#define DCRN_MALESR(base) ((base) + 0x1) /* Error Status */ +#define DCRN_MALIER(base) ((base) + 0x2) /* Interrupt Enable */ +#define DCRN_MALTXCARR(base) ((base) + 0x5) /* TX Channed Active Reset Register */ +#define DCRN_MALTXCASR(base) ((base) + 0x4) /* TX Channel Active Set Register */ +#define DCRN_MALTXDEIR(base) ((base) + 0x7) /* Tx Descriptor Error Interrupt */ +#define DCRN_MALTXEOBISR(base) ((base) + 0x6) /* Tx End of Buffer Interrupt Status */ +#define DCRN_MALRXCARR(base) ((base) + 0x11) /* RX Channed Active Reset Register */ +#define DCRN_MALRXCASR(base) ((base) + 0x10) /* RX Channel Active Set Register */ +#define DCRN_MALRXDEIR(base) ((base) + 0x13) /* Rx Descriptor Error Interrupt */ +#define DCRN_MALRXEOBISR(base) ((base) + 0x12) /* Rx End of Buffer Interrupt Status */ +#define DCRN_MALRXCTP0R(base) ((base) + 0x40) /* Channel Rx 0 Channel Table Pointer */ +#define DCRN_MALRXCTP1R(base) ((base) + 0x41) /* Channel Rx 1 Channel Table Pointer */ +#define DCRN_MALTXCTP0R(base) ((base) + 0x20) /* Channel Tx 0 Channel Table Pointer */ +#define DCRN_MALTXCTP1R(base) ((base) + 0x21) /* Channel Tx 1 Channel Table Pointer */ +#define DCRN_MALTXCTP2R(base) ((base) + 0x22) /* Channel Tx 2 Channel Table Pointer */ +#define DCRN_MALTXCTP3R(base) ((base) + 0x23) /* Channel Tx 3 Channel Table Pointer */ +#define DCRN_MALRCBS0(base) ((base) + 0x60) /* Channel Rx 0 Channel Buffer Size */ +#define DCRN_MALRCBS1(base) ((base) + 0x61) /* Channel Rx 1 Channel Buffer Size */ + + /* DCRN_MALCR */ +#define MALCR_MMSR 0x80000000 /* MAL Software reset */ +#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ +#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ +#define MALCR_PLBP_3 0x00C00000 /* highest */ +#define MALCR_GA 0x00200000 /* Guarded Active Bit */ +#define MALCR_OA 0x00100000 /* Ordered Active Bit */ +#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ +#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ +#define MALCR_PLBLT_2 0x00020000 +#define MALCR_PLBLT_3 0x00010000 +#define MALCR_PLBLT_4 0x00008000 +#define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */ +#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ +#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ +#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ +#define MALCR_LEA 0x00000002 /* Locked Error Active */ +#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ +/* DCRN_MALESR */ +#define MALESR_EVB 0x80000000 /* Error Valid Bit */ +#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ +#define MALESR_DE 0x00100000 /* Descriptor Error */ +#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ +#define MALESR_OTE 0x00040000 /* OPB Timeout Error */ +#define MALESR_OSE 0x00020000 /* OPB Slave Error */ +#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ +#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ +#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ +#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ +#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ +#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ +/* DCRN_MALIER */ +#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ +#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ +#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ +#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ +#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ +/* DCRN_MALTXEOBISR */ +#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ +#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ + +#ifdef DCRN_PLB0_BASE +#define DCRN_PLB0_BESR (DCRN_PLB0_BASE + 0x0) +#define DCRN_PLB0_BEAR (DCRN_PLB0_BASE + 0x2) +/* doesn't exist on stb03xxx? */ +#define DCRN_PLB0_ACR (DCRN_PLB0_BASE + 0x3) +#endif + +#ifdef DCRN_PLB1_BASE +#define DCRN_PLB1_BESR (DCRN_PLB1_BASE + 0x0) +#define DCRN_PLB1_BEAR (DCRN_PLB1_BASE + 0x1) +/* doesn't exist on stb03xxx? */ +#define DCRN_PLB1_ACR (DCRN_PLB1_BASE + 0x2) +#endif + +#ifdef DCRN_PLLMR_BASE +#define DCRN_PLLMR (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */ +#endif + +#ifdef DCRN_POB0_BASE +#define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0) +#define DCRN_POB0_BEAR (DCRN_POB0_BASE + 0x2) +#define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4) +#endif + +#define DCRN_UIC_SR(base) (base + 0x0) +#define DCRN_UIC_ER(base) (base + 0x2) +#define DCRN_UIC_CR(base) (base + 0x3) +#define DCRN_UIC_PR(base) (base + 0x4) +#define DCRN_UIC_TR(base) (base + 0x5) +#define DCRN_UIC_MSR(base) (base + 0x6) +#define DCRN_UIC_VR(base) (base + 0x7) +#define DCRN_UIC_VCR(base) (base + 0x8) + +#ifdef DCRN_SDRAM0_BASE +#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */ +#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */ +#endif + +#ifdef DCRN_OCM0_BASE +#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ +#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ +#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ +#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ +#endif + +#endif /* __ASM_IBM405_H__ */ +#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/platforms/ibm405gp.c cset-v2.4.20/arch/ppc/platforms/ibm405gp.c --- cset-v2.4.20~/arch/ppc/platforms/ibm405gp.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/platforms/ibm405gp.c 2004-11-01 22:35:09.000000000 +0900 @@ -0,0 +1,107 @@ +/* + * + * Copyright 2000-2001 MontaVista Software Inc. + * Original author: Armin Kuster akuster@mvista.com + * + * Module name: ibm405gp.c + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct ocp_func_emac_data ibm405gp_emac0_def = { + .zmii_idx = -1, /* ZMII device index */ + .zmii_mux = 0, /* ZMII input of this EMAC */ + .mal_idx = 0, /* MAL device index */ + .mal_rx_chan = 0, /* MAL rx channel number */ + .mal_tx1_chan = 0, /* MAL tx channel 1 number */ + .mal_tx2_chan = 1, /* MAL tx channel 2 number */ + .wol_irq = BL_MAC_WOL, /* WOL interrupt number */ + .mdio_idx = -1, /* No shared MDIO */ +}; + +static struct ocp_func_mal_data ibm405gp_mal0_def = { + .num_tx_chans = 2*EMAC_NUMS, /* Number of TX channels */ + .num_rx_chans = EMAC_NUMS, /* Number of RX channels */ +}; + +struct ocp_def core_ocp[] __initdata = { + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_OPB, + .index = 0, + .paddr = OPB_BASE_START, + .irq = OCP_IRQ_NA, + .pm = OCP_CPM_NA, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_16550, + .index = 0, + .paddr = UART0_IO_BASE, + .irq = UART0_INT, + .pm = IBM_CPM_UART0 + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_16550, + .index = 1, + .paddr = UART1_IO_BASE, + .irq = UART1_INT, + .pm = IBM_CPM_UART1 + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_IIC, + .paddr = IIC0_BASE, + .irq = IIC0_IRQ, + .pm = IBM_CPM_IIC0 + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_GPIO, + .paddr = GPIO0_BASE, + .irq = OCP_IRQ_NA, + .pm = IBM_CPM_GPIO0 + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_MAL, + .paddr = OCP_PADDR_NA, + .irq = OCP_IRQ_NA, + .pm = OCP_CPM_NA, + .additions = &ibm405gp_mal0_def, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_EMAC, + .index = 0, + .paddr = EMAC0_BASE, + .irq = BL_MAC_ETH0, + .pm = IBM_CPM_EMAC0, + .additions = &ibm405gp_emac0_def, + }, + { .vendor = OCP_VENDOR_INVALID + } +}; diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/platforms/ibm405gp.h cset-v2.4.20/arch/ppc/platforms/ibm405gp.h --- cset-v2.4.20~/arch/ppc/platforms/ibm405gp.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/platforms/ibm405gp.h 2004-11-01 22:35:09.000000000 +0900 @@ -0,0 +1,193 @@ +/* + * ibm405gp.h + * + * This was derived from the ppc4xx.h and all 405GP specific + * definition and board inclusions were moved here. + * + * Original author: Armin Kuster akuster@mvista.com + * Oct, 2001 + * + * + * Copyright 2001 MontaVista Softare Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifdef __KERNEL__ +#ifndef __ASM_IBM405GP_H__ +#define __ASM_IBM405GP_H__ + +#include + +/* ibm405.h is included at the bottom of this file */ + +/* PCI + * PCI Bridge config reg definitions + * see 17-19 of manual + */ + +#define PPC405_PCI_CONFIG_ADDR 0xeec00000 +#define PPC405_PCI_CONFIG_DATA 0xeec00004 + +#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */ + /* setbat */ +#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */ +#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */ +#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */ + +#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */ +#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */ +#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */ +#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */ + +#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE + +#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE) +#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR +#define PPC4xx_PCI_IO_SIZE ((uint)64*1024) +#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR) +#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR +#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024) +#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000) +#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR +#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024) +#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000) +#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR +#define PPC4xx_ONB_IO_SIZE ((uint)4*1024) + +#define OPB_BASE_START 0x40000000 +#define EBIU_BASE_START 0xF0100000 + +/* serial port defines */ +#define RS_TABLE_SIZE 2 + +#define UART0_INT 0 +#define UART1_INT 1 + +#define PCIL0_BASE 0xEF400000 +#define UART0_IO_BASE 0xEF600300 +#define UART1_IO_BASE 0xEF600400 +#define IIC0_BASE 0xEF600500 +#define OPB0_BASE 0xEF600600 +#define GPIO0_BASE 0xEF600700 +#define EMAC0_BASE 0xEF600800 +#define BL_MAC_WOL 9 /* WOL */ +#define BL_MAL_SERR 10 /* MAL SERR */ +#define BL_MAL_TXDE 13 /* MAL TXDE */ +#define BL_MAL_RXDE 14 /* MAL RXDE */ +#define BL_MAL_TXEOB 11 /* MAL TX EOB */ +#define BL_MAL_RXEOB 12 /* MAL RX EOB */ +#define BL_MAC_ETH0 15 /* MAC */ + +#define EMAC_NUMS 1 +#define IIC0_IRQ 2 +#define IIC1_IRQ 0 + +#define IIC_OWN 0x55 +#define IIC_CLOCK 50 +#define BD_EMAC_ADDR(e,i) bi_enetaddr[i] + +#define STD_UART_OP(num) \ + { 0, BASE_BAUD, 0, UART##num##_INT, \ + (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ + iomem_base: (u8 *)UART##num##_IO_BASE, \ + io_type: SERIAL_IO_MEM}, + +#if defined(CONFIG_UART0_TTYS0) +#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE +#define SERIAL_PORT_DFNS \ + STD_UART_OP(0) \ + STD_UART_OP(1) +#endif + +#if defined(CONFIG_UART0_TTYS1) +#define SERIAL_DEBUG_IO_BASE UART1_IO_BASE +#define SERIAL_PORT_DFNS \ + STD_UART_OP(1) \ + STD_UART_OP(0) +#endif + +/* DCR defines */ +#define DCRN_CHCR_BASE 0x0B1 +#define DCRN_CHPSR_BASE 0x0B4 +#define DCRN_CPMSR_BASE 0x0B8 +#define DCRN_CPMFR_BASE 0x0BA + +#define CHR0_U0EC 0x00000080 /* Select external clock for UART0 */ +#define CHR0_U1EC 0x00000040 /* Select external clock for UART1 */ +#define CHR0_UDIV 0x0000003E /* UART internal clock divisor */ +#define CHR1_CETE 0x00800000 /* CPU external timer enable */ + +#define DCRN_CHPSR_BASE 0x0B4 +#define PSR_PLL_FWD_MASK 0xC0000000 +#define PSR_PLL_FDBACK_MASK 0x30000000 +#define PSR_PLL_TUNING_MASK 0x0E000000 +#define PSR_PLB_CPU_MASK 0x01800000 +#define PSR_OPB_PLB_MASK 0x00600000 +#define PSR_PCI_PLB_MASK 0x00180000 +#define PSR_EB_PLB_MASK 0x00060000 +#define PSR_ROM_WIDTH_MASK 0x00018000 +#define PSR_ROM_LOC 0x00004000 +#define PSR_PCI_ASYNC_EN 0x00001000 +#define PSR_PCI_ARBIT_EN 0x00000400 + +#define IBM_CPM_IIC0 0x80000000 /* IIC interface */ +#define IBM_CPM_PCI 0x40000000 /* PCI bridge */ +#define IBM_CPM_CPU 0x20000000 /* processor core */ +#define IBM_CPM_DMA 0x10000000 /* DMA controller */ +#define IBM_CPM_OPB 0x08000000 /* PLB to OPB bridge */ +#define IBM_CPM_DCP 0x04000000 /* CodePack */ +#define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */ +#define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */ +#define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */ +#define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */ +#define IBM_CPM_UART0 0x00200000 /* serial port 0 */ +#define IBM_CPM_UART1 0x00100000 /* serial port 1 */ +#define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */ +#define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */ +#define IBM_CPM_EMAC0 0x00020000 /* on-chip ethernet MM unit */ +#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \ + | IBM_CPM_OPB | IBM_CPM_EBC \ + | IBM_CPM_SDRAM0 | IBM_CPM_PLB \ + | IBM_CPM_UIC | IBM_CPM_TMRCLK) + +#define DCRN_DMA0_BASE 0x100 +#define DCRN_DMA1_BASE 0x108 +#define DCRN_DMA2_BASE 0x110 +#define DCRN_DMA3_BASE 0x118 +#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ +#define DCRN_DMASR_BASE 0x120 +#define DCRN_EBC_BASE 0x012 +#define DCRN_DCP0_BASE 0x014 +#define DCRN_MAL_BASE 0x180 +#define DCRN_OCM0_BASE 0x018 +#define DCRN_PLB0_BASE 0x084 +#define DCRN_PLLMR_BASE 0x0B0 +#define DCRN_POB0_BASE 0x0A0 +#define DCRN_SDRAM0_BASE 0x010 +#define DCRN_UIC0_BASE 0x0C0 +#define UIC0 DCRN_UIC0_BASE + +#include + +#endif /* __ASM_IBM405GP_H__ */ +#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/platforms/ibm440gp.c cset-v2.4.20/arch/ppc/platforms/ibm440gp.c --- cset-v2.4.20~/arch/ppc/platforms/ibm440gp.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/platforms/ibm440gp.c 2004-11-01 22:35:09.000000000 +0900 @@ -0,0 +1,129 @@ +/* + * arch/ppc/platforms/ibm440gp.c + * + * PPC440GP I/O descriptions + * + * Matt Porter + * Copyright 2002-2003 MontaVista Software Inc. + * + * Eugene Surovegin or + * Copyright (c) 2003 Zultys Technologies + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include +#include +#include +#include + +#if defined(EMAC_NUMS) && EMAC_NUMS > 0 +u32 emac_phy_map[EMAC_NUMS]; +EXPORT_SYMBOL(emac_phy_map); +#endif + +static struct ocp_func_emac_data ibm440gp_emac0_def = { + .zmii_idx = 0, /* ZMII device index */ + .zmii_mux = 0, /* ZMII input of this EMAC */ + .mal_idx = 0, /* MAL device index */ + .mal_rx_chan = 0, /* MAL rx channel number */ + .mal_tx1_chan = 0, /* MAL tx channel 1 number */ + .mal_tx2_chan = 1, /* MAL tx channel 2 number */ + .wol_irq = BL_MAC_WOL, /* WOL interrupt number */ + .mdio_idx = -1, /* No shared MDIO */ +}; + +static struct ocp_func_emac_data ibm440gp_emac1_def = { + .zmii_idx = 0, /* ZMII device index */ + .zmii_mux = 1, /* ZMII input of this EMAC */ + .mal_idx = 0, /* MAL device index */ + .mal_rx_chan = 1, /* MAL rx channel number */ + .mal_tx1_chan = 2, /* MAL tx channel 1 number */ + .mal_tx2_chan = 3, /* MAL tx channel 2 number */ + .wol_irq = BL_MAC_WOL1, /* WOL interrupt number */ + .mdio_idx = -1, /* No shared MDIO */ +}; + +static struct ocp_func_mal_data ibm440gp_mal0_def = { + .num_tx_chans = 2*EMAC_NUMS, /* Number of TX channels */ + .num_rx_chans = EMAC_NUMS, /* Number of RX channels */ +}; + +struct ocp_def core_ocp[] __initdata = { + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_OPB, + .index = 0, + .paddr = PPC440GP_OPB_BASE_START, + .irq = OCP_IRQ_NA, + .pm = OCP_CPM_NA, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_16550, + .index = 0, + .paddr = PPC440GP_UART0_ADDR, + .irq = UART0_INT, + .pm = IBM_CPM_UART0, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_16550, + .index = 1, + .paddr = PPC440GP_UART1_ADDR, + .irq = UART1_INT, + .pm = IBM_CPM_UART1, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_IIC, + .index = 0, + .paddr = PPC440GP_IIC0_ADDR, + .irq = IIC0_IRQ, + .pm = IBM_CPM_IIC0, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_IIC, + .index = 1, + .paddr = PPC440GP_IIC1_ADDR, + .irq = IIC1_IRQ, + .pm = IBM_CPM_IIC1, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_GPIO, + .index = 0, + .paddr = PPC440GP_GPIO0_ADDR, + .irq = OCP_IRQ_NA, + .pm = IBM_CPM_GPIO0, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_MAL, + .paddr = OCP_PADDR_NA, + .irq = OCP_IRQ_NA, + .pm = OCP_CPM_NA, + .additions = &ibm440gp_mal0_def, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_EMAC, + .index = 0, + .paddr = PPC440GP_EMAC0_ADDR, + .irq = BL_MAC_ETH0, + .pm = OCP_CPM_NA, + .additions = &ibm440gp_emac0_def, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_EMAC, + .index = 1, + .paddr = PPC440GP_EMAC1_ADDR, + .irq = BL_MAC_ETH1, + .pm = OCP_CPM_NA, + .additions = &ibm440gp_emac1_def, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_ZMII, + .paddr = PPC440GP_ZMII_ADDR, + .irq = OCP_IRQ_NA, + .pm = OCP_CPM_NA, + }, + { .vendor = OCP_VENDOR_INVALID + } +}; diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/platforms/ibm440gp.h cset-v2.4.20/arch/ppc/platforms/ibm440gp.h --- cset-v2.4.20~/arch/ppc/platforms/ibm440gp.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/platforms/ibm440gp.h 2004-11-01 22:35:10.000000000 +0900 @@ -0,0 +1,103 @@ +/* + * arch/ppc/platforms/ibm440gp.h + * + * PPC440GP definitions + * + * Roland Dreier + * + * Copyright 2002 Roland Dreier + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This file contains code that was originally in the files ibm44x.h + * and ebony.h, which were written by Matt Porter of MontaVista Software Inc. + */ + +#ifdef __KERNEL__ +#ifndef __PPC_PLATFORMS_IBM440GP_H +#define __PPC_PLATFORMS_IBM440GP_H + +#include + +#include + +#define EMAC_NUMS 2 +#define UART_NUMS 2 +#define ZMII_NUMS 1 +#define IIC_NUMS 2 +#define IIC0_IRQ 2 +#define IIC1_IRQ 3 +#define GPIO_NUMS 1 + +/* UART location */ +#define PPC440GP_UART0_ADDR 0x0000000140000200ULL +#define PPC440GP_UART1_ADDR 0x0000000140000300ULL +#define UART0_INT 0 +#define UART1_INT 1 + +/* EMAC location */ +#define PPC440GP_EMAC0_ADDR 0x0000000140000800ULL +#define PPC440GP_EMAC1_ADDR 0x0000000140000900ULL +#define PPC440GP_EMAC_SIZE 0x70 + +/* EMAC IRQ's */ +#define BL_MAC_WOL 61 /* WOL */ +#define BL_MAC_WOL1 63 /* WOL */ +#define BL_MAL_SERR 32 /* MAL SERR */ +#define BL_MAL_TXDE 33 /* MAL TXDE */ +#define BL_MAL_RXDE 34 /* MAL RXDE */ +#define BL_MAL_TXEOB 10 /* MAL TX EOB */ +#define BL_MAL_RXEOB 11 /* MAL RX EOB */ +#define BL_MAC_ETH0 60 /* MAC */ +#define BL_MAC_ETH1 62 /* MAC */ + +/* ZMII location */ +#define PPC440GP_ZMII_ADDR 0x0000000140000780ULL +#define PPC440GP_ZMII_SIZE 0x0c + +/* I2C location */ +#define PPC440GP_IIC0_ADDR 0x40000400 +#define PPC440GP_IIC1_ADDR 0x40000500 + +/* GPIO location */ +#define PPC440GP_GPIO0_ADDR 0x0000000140000700ULL + +/* Clock and Power Management */ +#define IBM_CPM_IIC0 0x80000000 /* IIC interface */ +#define IBM_CPM_IIC1 0x40000000 /* IIC interface */ +#define IBM_CPM_PCI 0x20000000 /* PCI bridge */ +#define IBM_CPM_CPU 0x02000000 /* processor core */ +#define IBM_CPM_DMA 0x01000000 /* DMA controller */ +#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */ +#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */ +#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */ +#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */ +#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */ +#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */ +#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */ +#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */ +#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */ +#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */ +#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */ +#define IBM_CPM_UART0 0x00000200 /* serial port 0 */ +#define IBM_CPM_UART1 0x00000100 /* serial port 1 */ +#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */ +#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */ + +#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \ + | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \ + | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \ + | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI) + +#define PPC440GP_OPB_BASE_START 0x0000000140000000ULL + +/* + * Serial port defines + */ +#define RS_TABLE_SIZE 2 + +#endif /* __PPC_PLATFORMS_IBM440GP_H */ +#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/platforms/ibm440gx.c cset-v2.4.20/arch/ppc/platforms/ibm440gx.c --- cset-v2.4.20~/arch/ppc/platforms/ibm440gx.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/platforms/ibm440gx.c 2004-11-01 22:35:10.000000000 +0900 @@ -0,0 +1,129 @@ +/* + * arch/ppc/platforms/4xx/ibm440gx.c + * + * PPC440GX I/O descriptions + * + * Matt Porter + * Copyright 2002-2003 MontaVista Software Inc. + * + * Eugene Surovegin or + * Copyright (c) 2003 Zultys Technologies + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include +#include +#include +#include + +#if defined(EMAC_NUMS) && EMAC_NUMS > 0 +u32 emac_phy_map[EMAC_NUMS]; +EXPORT_SYMBOL(emac_phy_map); +#endif + +static struct ocp_func_emac_data ibm440gx_emac0_def = { + .zmii_idx = 0, /* ZMII device index */ + .zmii_mux = 0, /* ZMII input of this EMAC */ + .mal_idx = 0, /* MAL device index */ + .mal_rx_chan = 0, /* MAL rx channel number */ + .mal_tx1_chan = 0, /* MAL tx channel 1 number */ + .mal_tx2_chan = -1, /* MAL tx channel 2 number */ + .wol_irq = BL_MAC_WOL, /* WOL interrupt number */ + .mdio_idx = -1, /* No shared MDIO */ +}; + +static struct ocp_func_emac_data ibm440gx_emac1_def = { + .zmii_idx = 0, /* ZMII device index */ + .zmii_mux = 1, /* ZMII input of this EMAC */ + .mal_idx = 0, /* MAL device index */ + .mal_rx_chan = 1, /* MAL rx channel number */ + .mal_tx1_chan = 1, /* MAL tx channel 1 number */ + .mal_tx2_chan = -1, /* MAL tx channel 2 number */ + .wol_irq = BL_MAC_WOL1, /* WOL interrupt number */ + .mdio_idx = -1, /* No shared MDIO */ +}; + +static struct ocp_func_mal_data ibm440gx_mal0_def = { + .num_tx_chans = 2*EMAC_NUMS, /* Number of TX channels */ + .num_rx_chans = EMAC_NUMS, /* Number of RX channels */ +}; + +struct ocp_def core_ocp[] __initdata = { + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_OPB, + .index = 0, + .paddr = PPC440GX_OPB_BASE_START, + .irq = OCP_IRQ_NA, + .pm = OCP_CPM_NA, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_16550, + .index = 0, + .paddr = PPC440GX_UART0_ADDR, + .irq = UART0_INT, + .pm = IBM_CPM_UART0, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_16550, + .index = 1, + .paddr = PPC440GX_UART1_ADDR, + .irq = UART1_INT, + .pm = IBM_CPM_UART1, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_IIC, + .index = 0, + .paddr = PPC440GX_IIC0_ADDR, + .irq = IIC0_IRQ, + .pm = IBM_CPM_IIC0, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_IIC, + .index = 1, + .paddr = PPC440GX_IIC1_ADDR, + .irq = IIC1_IRQ, + .pm = IBM_CPM_IIC1, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_GPIO, + .index = 0, + .paddr = PPC440GX_GPIO0_ADDR, + .irq = OCP_IRQ_NA, + .pm = IBM_CPM_GPIO0, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_MAL, + .paddr = OCP_PADDR_NA, + .irq = OCP_IRQ_NA, + .pm = OCP_CPM_NA, + .additions = &ibm440gx_mal0_def, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_EMAC, + .index = 0, + .paddr = PPC440GX_EMAC0_ADDR, + .irq = BL_MAC_ETH0, + .pm = OCP_CPM_NA, + .additions = &ibm440gx_emac0_def, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_EMAC, + .index = 1, + .paddr = PPC440GX_EMAC1_ADDR, + .irq = BL_MAC_ETH1, + .pm = OCP_CPM_NA, + .additions = &ibm440gx_emac1_def, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_ZMII, + .paddr = PPC440GX_ZMII_ADDR, + .irq = OCP_IRQ_NA, + .pm = OCP_CPM_NA, + }, + { .vendor = OCP_VENDOR_INVALID + } +}; diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/platforms/ibm440gx.h cset-v2.4.20/arch/ppc/platforms/ibm440gx.h --- cset-v2.4.20~/arch/ppc/platforms/ibm440gx.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/platforms/ibm440gx.h 2004-11-01 22:35:10.000000000 +0900 @@ -0,0 +1,123 @@ +/* + * arch/ppc/platforms/ibm440gx.h + * + * PPC440GX definitions + * + * Matt Porter + * + * Copyright 2002 Roland Dreier + * Copyright 2003 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifdef __KERNEL__ +#ifndef __PPC_PLATFORMS_IBM440GX_H +#define __PPC_PLATFORMS_IBM440GX_H + +#include + +#include + +/* UART */ +#define PPC440GX_UART0_ADDR 0x0000000140000200 +#define PPC440GX_UART1_ADDR 0x0000000140000300 +#define UART0_INT 0 +#define UART1_INT 1 + +/* EMAC */ +#define PPC440GX_EMAC0_ADDR 0x0000000140000800 +#define PPC440GX_EMAC1_ADDR 0x0000000140000900 +#define PPC440GX_EMAC2_ADDR 0x0000000140000C00 +#define PPC440GX_EMAC3_ADDR 0x0000000140000E00 +#define PPC440GX_EMAC_SIZE 0xFC +#define EMAC_NUMS 2 +#define BL_MAC_WOL 61 /* WOL */ +#define BL_MAC_WOL1 63 /* WOL */ +#define BL_MAC_WOL2 65 /* WOL */ +#define BL_MAC_WOL3 67 /* WOL */ +#define BL_MAL_SERR 32 /* MAL SERR */ +#define BL_MAL_TXDE 33 /* MAL TXDE */ +#define BL_MAL_RXDE 34 /* MAL RXDE */ +#define BL_MAL_TXEOB 10 /* MAL TX EOB */ +#define BL_MAL_RXEOB 11 /* MAL RX EOB */ +#define BL_MAC_ETH0 60 /* MAC */ +#define BL_MAC_ETH1 62 /* MAC */ +#define BL_MAC_ETH2 64 /* MAC */ +#define BL_MAC_ETH3 66 /* MAC */ +#define BL_TAH0 68 /* TAH 0 */ +#define BL_TAH1 69 /* TAH 1 */ + +/* TAH */ +#define PPC440GX_TAH0_ADDR 0x0000000140000B00 +#define PPC440GX_TAH1_ADDR 0x0000000140000D00 +#define PPC440GX_TAH_SIZE 0xFC + +/* ZMII */ +#define PPC440GX_ZMII_ADDR 0x0000000140000780 +#define PPC440GX_ZMII_SIZE 0x0c + +/* RGMII */ +#define PPC440GX_RGMII_ADDR 0x0000000140000790 +#define PPC440GX_RGMII_SIZE 0x0c + +/* IIC */ +#define PPC440GX_IIC0_ADDR 0x40000400 +#define PPC440GX_IIC1_ADDR 0x40000500 +#define IIC0_IRQ 2 +#define IIC1_IRQ 3 + +/* GPIO */ +#define PPC440GX_GPIO0_ADDR 0x0000000140000700 + +/* Clock and Power Management */ +#define IBM_CPM_IIC0 0x80000000 /* IIC interface */ +#define IBM_CPM_IIC1 0x40000000 /* IIC interface */ +#define IBM_CPM_PCI 0x20000000 /* PCI bridge */ +#define IBM_CPM_RGMII 0x10000000 /* RGMII */ +#define IBM_CPM_TAHOE0 0x08000000 /* TAHOE 0 */ +#define IBM_CPM_TAHOE1 0x04000000 /* TAHOE 1 */ +#define IBM_CPM_CPU 0x02000000 /* processor core */ +#define IBM_CPM_DMA 0x01000000 /* DMA controller */ +#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */ +#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */ +#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */ +#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */ +#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */ +#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */ +#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */ +#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */ +#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */ +#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */ +#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */ +#define IBM_CPM_UART0 0x00000200 /* serial port 0 */ +#define IBM_CPM_UART1 0x00000100 /* serial port 1 */ +#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */ +#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */ +#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */ +#define IBM_CPM_EMAC1 0x00000010 /* EMAC 1 */ +#define IBM_CPM_EMAC2 0x00000008 /* EMAC 2 */ +#define IBM_CPM_EMAC3 0x00000004 /* EMAC 3 */ + +#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \ + | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \ + | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \ + | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \ + | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \ + | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \ + | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 ) + +/* OPB */ +#define PPC440GX_OPB_BASE_START 0x0000000140000000 + +/* + * Serial port defines + */ +#define RS_TABLE_SIZE 2 + +#endif /* __PPC_PLATFORMS_IBM440GX_H */ +#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/platforms/ibm_ocp.h cset-v2.4.20/arch/ppc/platforms/ibm_ocp.h --- cset-v2.4.20~/arch/ppc/platforms/ibm_ocp.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/platforms/ibm_ocp.h 2004-11-01 22:35:10.000000000 +0900 @@ -0,0 +1,152 @@ +/* + * arch/ppc/platforms/ibm_ocp.h + * + * Definitions for the on-chip peripherals on the IBM + * PPC405GP embedded processor. + * + * Copyright 2001 MontaVista Softare Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifdef __KERNEL__ +#ifndef __ASM_IBM_OCP_H__ +#define __ASM_IBM_OCP_H__ + +#ifndef __ASSEMBLY__ +#include + +// +// TODO: DEPRECATE THIS FILE ! +// + + /* PCI 32 */ + +struct pmm_regs { + u32 la; + u32 ma; + u32 pcila; + u32 pciha; +}; + +typedef struct pcil0_regs { + struct pmm_regs pmm[3]; + u32 ptm1ms; + u32 ptm1la; + u32 ptm2ms; + u32 ptm2la; +} pci0_t; + +/* Serial Ports */ + +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +typedef struct NS16550 { + u8 rbr; /* 0 */ + u8 ier; /* 1 */ + u8 fcr; /* 2 */ + u8 lcr; /* 3 */ + u8 mcr; /* 4 */ + u8 lsr; /* 5 */ + u8 msr; /* 6 */ + u8 scr; /* 7 */ +} uart_t; + +/* I2c */ +typedef struct iic_regs { + u16 mdbuf; + u16 sbbuf; + u8 lmadr; + u8 hmadr; + u8 cntl; + u8 mdcntl; + u8 sts; + u8 extsts; + u8 lsadr; + u8 hsadr; + u8 clkdiv; + u8 intmsk; + u8 xfrcnt; + u8 xtcntlss; + u8 directcntl; +} iic_t; + +/* OPB arbiter */ +typedef struct opb { + u8 pr; + u8 cr; +} opb_t; + +/* General purpose i/o */ + +typedef struct gpio_regs { + u32 or; + u32 tcr; + u32 pad[4]; + u32 odr; + u32 ir; +} gpio_t; + +/* Structure of the memory mapped IDE control. +*/ +typedef struct ide_regs { + unsigned int si_stat; /* IDE status */ + unsigned int si_intenable; /* IDE interrupt enable */ + unsigned int si_control; /* IDE control */ + unsigned int pad0[0x3d]; + unsigned int si_c0rt; /* Chan 0 Register transfer timing */ + unsigned int si_c0fpt; /* Chan 0 Fast PIO transfer timing */ + unsigned int si_c0timo; /* Chan 0 timeout */ + unsigned int pad1[2]; + unsigned int si_c0d0u; /* Chan 0 UDMA transfer timing */ +#define si_c0d0m si_c0d0u /* Chan 0 Multiword DMA timing */ + unsigned int pad2; + unsigned int si_c0d1u; /* Chan 0 dev 1 UDMA timing */ +#define si_c0d1m si_c0d1u /* Chan 0 dev 1 Multiword DMA timing */ + unsigned int si_c0c; /* Chan 0 Control */ + unsigned int si_c0s0; /* Chan 0 Status 0 */ + unsigned int si_c0ie; /* Chan 0 Interrupt Enable */ + unsigned int si_c0s1; /* Chan 0 Status 0 */ + unsigned int pad4[4]; + unsigned int si_c0dcm; /* Chan 0 DMA Command */ + unsigned int si_c0tb; /* Chan 0 PRD Table base address */ + unsigned int si_c0dct; /* Chan 0 DMA Count */ + unsigned int si_c0da; /* Chan 0 DMA Address */ + unsigned int si_c0sr; /* Chan 0 Slew Rate Output Control */ + unsigned char pad5[0xa2]; + unsigned short si_c0adc; /* Chan 0 Alt status/control */ + unsigned char si_c0d; /* Chan 0 data */ + unsigned char si_c0ef; /* Chan 0 error/features */ + unsigned char si_c0sct; /* Chan 0 sector count */ + unsigned char si_c0sn; /* Chan 0 sector number */ + unsigned char si_c0cl; /* Chan 0 cylinder low */ + unsigned char si_c0ch; /* Chan 0 cylinder high */ + unsigned char si_c0dh; /* Chan 0 device/head */ + unsigned char si_c0scm; /* Chan 0 status/command */ +} ide_t; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_IBM_OCP_H__ */ +#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/platforms/ocotea.c cset-v2.4.20/arch/ppc/platforms/ocotea.c --- cset-v2.4.20~/arch/ppc/platforms/ocotea.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/platforms/ocotea.c 2004-11-02 17:52:52.000000000 +0900 @@ -0,0 +1,461 @@ +/* + * arch/ppc/platforms/ocotea.c + * + * Ocotea board specific routines + * + * Matt Porter + * + * Copyright 2003 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +extern void abort(void); +extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode); +extern int pckbd_getkeycode(unsigned int scancode); +extern int pckbd_translate(unsigned char scancode, unsigned char *keycode, + char raw_mode); +extern void gen550_progress(char *, unsigned short); +extern void gen550_init(int, struct serial_struct *); + +/* Global Variables */ +unsigned char __res[sizeof (bd_t)]; + +static void __init +ocotea_calibrate_decr(void) +{ + unsigned int freq; + + freq = OCOTEA_SYSCLK; + + tb_ticks_per_jiffy = freq / HZ; + tb_to_us = mulhwu_scale_factor(freq, 1000000); + + /* Set the time base to zero */ + mtspr(SPRN_TBWL, 0); + mtspr(SPRN_TBWU, 0); + + /* Clear any pending timer interrupts */ + mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS); + + /* Enable decrementer interrupt */ + mtspr(SPRN_TCR, TCR_DIE); +} + +static int +ocotea_show_cpuinfo(struct seq_file *m) +{ + ibm440gx_show_cpuinfo(m); + seq_printf(m, "vendor\t\t: IBM\n"); + seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n"); + + return 0; +} + +static inline int +ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) +{ + static char pci_irq_table[][4] = + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + { + { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */ + { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */ + { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */ + { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */ + }; + + const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; + return PCI_IRQ_TABLE_LOOKUP; +} + +#define PCIX_READW(offset) \ + (readw((u32)pcix_reg_base+offset)) + +#define PCIX_WRITEW(value, offset) \ + (writew(value, (u32)pcix_reg_base+offset)) + +#define PCIX_WRITEL(value, offset) \ + (writel(value, (u32)pcix_reg_base+offset)) + +/* + * FIXME: This is only here to "make it work". This will move + * to a ibm_pcix.c which will contain a generic IBM PCIX bridge + * configuration library. -Matt + */ +static void __init +ocotea_setup_pcix(void) +{ + void *pcix_reg_base; + + pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX0_REG_SIZE); + + /* Enable PCIX0 I/O, Mem, and Busmaster cycles */ + PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND); + + /* Disable all windows */ + PCIX_WRITEL(0, PCIX0_POM0SA); + PCIX_WRITEL(0, PCIX0_POM1SA); + PCIX_WRITEL(0, PCIX0_POM2SA); + PCIX_WRITEL(0, PCIX0_PIM0SA); + PCIX_WRITEL(0, PCIX0_PIM0SAH); + PCIX_WRITEL(0, PCIX0_PIM1SA); + PCIX_WRITEL(0, PCIX0_PIM2SA); + PCIX_WRITEL(0, PCIX0_PIM2SAH); + + /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */ + PCIX_WRITEL(0x00000003, PCIX0_POM0LAH); + PCIX_WRITEL(0x80000000, PCIX0_POM0LAL); + PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH); + PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL); + PCIX_WRITEL(0x80000001, PCIX0_POM0SA); + + /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ + PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); + PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); + PCIX_WRITEL(0x80000007, PCIX0_PIM0SA); + + eieio(); +} + +static void __init +ocotea_setup_hose(void) +{ + struct pci_controller *hose; + + /* Configure windows on the PCI-X host bridge */ + ocotea_setup_pcix(); + + hose = pcibios_alloc_controller(); + + if (!hose) + return; + + hose->first_busno = 0; + hose->last_busno = 0xff; + + hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET; + + pci_init_resource(&hose->io_resource, + OCOTEA_PCI_LOWER_IO, + OCOTEA_PCI_UPPER_IO, + IORESOURCE_IO, + "PCI host bridge"); + + pci_init_resource(&hose->mem_resources[0], + OCOTEA_PCI_LOWER_MEM, + OCOTEA_PCI_UPPER_MEM, + IORESOURCE_MEM, + "PCI host bridge"); + + hose->io_space.start = OCOTEA_PCI_LOWER_IO; + hose->io_space.end = OCOTEA_PCI_UPPER_IO; + hose->mem_space.start = OCOTEA_PCI_LOWER_MEM; + hose->mem_space.end = OCOTEA_PCI_UPPER_MEM; + isa_io_base = + (unsigned long)ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE); + hose->io_base_virt = (void *)isa_io_base; + + setup_indirect_pci(hose, + OCOTEA_PCI_CFGA_PLB32, + OCOTEA_PCI_CFGD_PLB32); + hose->set_cfg_type = 1; + + hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); + + ppc_md.pci_swizzle = common_swizzle; + ppc_md.pci_map_irq = ocotea_map_irq; +} + + +TODC_ALLOC(); + +static void __init +ocotea_early_serial_map(const struct ibm44x_clocks* clks) +{ + struct serial_struct serial_req; + + /* Setup ioremapped serial port access */ + memset(&serial_req, 0, sizeof(serial_req)); + serial_req.line = 0; + serial_req.baud_base = clks->uart0 / 16; + serial_req.port = 0; + serial_req.irq = 0; + serial_req.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; + serial_req.io_type = SERIAL_IO_MEM; + serial_req.iomem_base = ioremap64(PPC440GX_UART0_ADDR, 8); + serial_req.iomem_reg_shift = 0; + +#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) + /* Configure debug serial access */ + gen550_init(0, &serial_req); +#endif + + if (early_serial_setup(&serial_req) != 0) { + printk("Early serial init of port 0 failed\n"); + } + + /* Assume early_serial_setup() doesn't modify serial_req */ + serial_req.line = 1; + serial_req.baud_base = clks->uart1 / 16; + serial_req.port = 1; + serial_req.irq = 1; + serial_req.iomem_base = ioremap64(PPC440GX_UART1_ADDR, 8); + +#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) + /* Configure debug serial access */ + gen550_init(1, &serial_req); +#endif + + if (early_serial_setup(&serial_req) != 0) { + printk("Early serial init of port 1 failed\n"); + } +} + +static void __init +ocotea_setup_arch(void) +{ + unsigned char *addr; + unsigned long long mac64; + bd_t *bip = (bd_t *) __res; + struct ibm44x_clocks clocks; + + /* Retrieve MAC addresses from flash */ + addr = ioremap64(OCOTEA_MAC_BASE, OCOTEA_MAC_SIZE); + mac64 = simple_strtoull(addr, 0, 16); + memcpy(bip->bi_enetaddr[0], (char *)&mac64+2, 6); + mac64 = simple_strtoull(addr+OCOTEA_MAC1_OFFSET, 0, 16); + memcpy(bip->bi_enetaddr[1], (char *)&mac64+2, 6); + iounmap(addr); + + /* Set EMAC PHY map to not probe address 0x00 */ + emac_phy_map[0] = 0x00000001; + emac_phy_map[1] = 0x00000001; + +#if !defined(CONFIG_BDI_SWITCH) + /* + * The Abatron BDI JTAG debugger does not tolerate others + * mucking with the debug registers. + */ + mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM)); +#endif + /* + * Determine various clocks. + * To be completely correct we should get SysClk + * from FPGA, because it can be changed by on-board switches + * --ebs + */ + ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200); + bip->bi_opb_busfreq = clocks.opb; + + /* Use IIC in standard (100 kHz) mode */ + bip->bi_iic_fast[0] = bip->bi_iic_fast[1] = 0; + + /* Setup TODC access */ + TODC_INIT(TODC_TYPE_DS1743, + 0, + 0, + ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE), + 8); + + /* init to some ~sane value until calibrate_delay() runs */ + loops_per_jiffy = 50000000/HZ; + + /* Setup PCI host bridge */ + ocotea_setup_hose(); + +#ifdef CONFIG_BLK_DEV_INITRD + if (initrd_start) + ROOT_DEV = to_kdev_t(0x0100); /* /dev/ram */ + else +#endif +#ifdef CONFIG_ROOT_NFS + ROOT_DEV = to_kdev_t(0x00ff); /* /dev/nfs */ +#else + ROOT_DEV = to_kdev_t(0x0301); /* /dev/hda1 */ +#endif + +#ifdef CONFIG_VT + conswitchp = &dummy_con; +#endif + + ocotea_early_serial_map(&clocks); + + /* Identify the system */ + printk("IBM Ocotea port (MontaVista Software, Inc. )\n"); +} + +static void +ocotea_restart(char *cmd) +{ + local_irq_disable(); + abort(); +} + +static void +ocotea_power_off(void) +{ + local_irq_disable(); + for(;;); +} + +static void +ocotea_halt(void) +{ + local_irq_disable(); + for(;;); +} + +/* + * Read the 440GX memory controller to get size of system memory. + */ +static unsigned long __init +ocotea_find_end_of_memory(void) +{ + u32 i, bank_config; + u32 mem_size = 0; + + for (i=0; i<4; i++) + { + switch (i) + { + case 0: + mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR); + break; + case 1: + mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR); + break; + case 2: + mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR); + break; + case 3: + mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR); + break; + } + + bank_config = mfdcr(DCRN_SDRAM0_CFGDATA); + + if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE)) + continue; + switch (SDRAM_CONFIG_BANK_SIZE(bank_config)) + { + case SDRAM_CONFIG_SIZE_8M: + mem_size += PPC44x_MEM_SIZE_8M; + break; + case SDRAM_CONFIG_SIZE_16M: + mem_size += PPC44x_MEM_SIZE_16M; + break; + case SDRAM_CONFIG_SIZE_32M: + mem_size += PPC44x_MEM_SIZE_32M; + break; + case SDRAM_CONFIG_SIZE_64M: + mem_size += PPC44x_MEM_SIZE_64M; + break; + case SDRAM_CONFIG_SIZE_128M: + mem_size += PPC44x_MEM_SIZE_128M; + break; + case SDRAM_CONFIG_SIZE_256M: + mem_size += PPC44x_MEM_SIZE_256M; + break; + case SDRAM_CONFIG_SIZE_512M: + mem_size += PPC44x_MEM_SIZE_512M; + break; + } + } + return mem_size; +} + +static void __init +ocotea_init_irq(void) +{ + int i; + + /* Enable PPC440GP interrupt compatibility mode */ + SDR_WRITE(DCRN_SDR_MFR,SDR_READ(DCRN_SDR_MFR) | DCRN_SDR_MFR_PCM); + + ppc4xx_pic_init(); + + for (i = 0; i < NR_IRQS; i++) + irq_desc[i].handler = ppc4xx_pic; +} + +void __init platform_init(unsigned long r3, unsigned long r4, + unsigned long r5, unsigned long r6, unsigned long r7) +{ + parse_bootinfo(find_bootinfo()); + + /* Disable L2-Cache due to hardware issues */ + ibm440gx_l2c_disable(); + + ppc_md.setup_arch = ocotea_setup_arch; + ppc_md.show_cpuinfo = ocotea_show_cpuinfo; + ppc_md.init_IRQ = ocotea_init_irq; + ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ + + ppc_md.find_end_of_memory = ocotea_find_end_of_memory; + + ppc_md.restart = ocotea_restart; + ppc_md.power_off = ocotea_power_off; + ppc_md.halt = ocotea_halt; + + ppc_md.calibrate_decr = ocotea_calibrate_decr; + ppc_md.time_init = todc_time_init; + ppc_md.set_rtc_time = todc_set_rtc_time; + ppc_md.get_rtc_time = todc_get_rtc_time; + + ppc_md.nvram_read_val = todc_direct_read_val; + ppc_md.nvram_write_val = todc_direct_write_val; +#if defined(CONFIG_VT) + ppc_md.kbd_setkeycode = pckbd_setkeycode; + ppc_md.kbd_getkeycode = pckbd_getkeycode; + ppc_md.kbd_translate = pckbd_translate; + ppc_md.kbd_unexpected_up = pckbd_unexpected_up; + ppc_md.kbd_leds = pckbd_leds; + ppc_md.kbd_init_hw = 0; +#endif + +#ifdef CONFIG_SERIAL_TEXT_DEBUG + ppc_md.progress = gen550_progress; +#endif /* CONFIG_SERIAL_TEXT_DEBUG */ +#ifdef CONFIG_KGDB + ppc_md.early_serial_map = ocotea_early_serial_map; +#endif +} diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/platforms/ocotea.h cset-v2.4.20/arch/ppc/platforms/ocotea.h --- cset-v2.4.20~/arch/ppc/platforms/ocotea.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/arch/ppc/platforms/ocotea.h 2004-11-02 17:38:17.000000000 +0900 @@ -0,0 +1,87 @@ +/* + * arch/ppc/platforms/ocotea.h + * + * Ocotea board definitions + * + * Matt Porter + * + * Copyright 2003 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifdef __KERNEL__ +#ifndef __ASM_OCOTEA_H__ +#define __ASM_OCOTEA_H__ + +#include +#include + +/* F/W TLB mapping used in bootloader glue to reset EMAC */ +#define PPC44x_EMAC0_MR0 0xE0000800 + +/* Location of MAC addresses in firmware */ +#define OCOTEA_MAC_BASE (OCOTEA_SMALL_FLASH_HIGH+0xb0500) +#define OCOTEA_MAC_SIZE 0x200 +#define OCOTEA_MAC1_OFFSET 0x100 + +/* Default clock rate */ +#define OCOTEA_SYSCLK 25000000 + +/* RTC/NVRAM location */ +#define OCOTEA_RTC_ADDR 0x0000000148000000ULL +#define OCOTEA_RTC_SIZE 0x2000 + +/* Flash */ +#define OCOTEA_FPGA_ADDR 0x0000000148300000ULL +#define OCOTEA_BOOT_LARGE_FLASH(x) (x & 0x40) +#define OCOTEA_SMALL_FLASH_LOW 0x00000001ff900000ULL +#define OCOTEA_SMALL_FLASH_HIGH 0x00000001fff00000ULL +#define OCOTEA_SMALL_FLASH_SIZE 0x100000 +#define OCOTEA_LARGE_FLASH_LOW 0x00000001ff800000ULL +#define OCOTEA_LARGE_FLASH_HIGH 0x00000001ffc00000ULL +#define OCOTEA_LARGE_FLASH_SIZE 0x400000 + +/* + * Serial port defines + */ +#define RS_TABLE_SIZE 2 + +/* OpenBIOS defined UART mappings, used before early_serial_setup */ +#define UART0_IO_BASE (u8 *) 0xE0000200 +#define UART1_IO_BASE (u8 *) 0xE0000300 + +/* This value is used only to fill something in STD_UART_OP definition, + actual value is determined in ocotea_early_serial_map. --ebs +*/ +#define BASE_BAUD 11059200/16 +#define STD_UART_OP(num) \ + { 0, BASE_BAUD, 0, UART##num##_INT, \ + (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ + iomem_base: UART##num##_IO_BASE, \ + io_type: SERIAL_IO_MEM}, + +#define SERIAL_PORT_DFNS \ + STD_UART_OP(0) \ + STD_UART_OP(1) + +/* PCI support */ +#define OCOTEA_PCI_LOWER_IO 0x00000000 +#define OCOTEA_PCI_UPPER_IO 0x0000ffff +#define OCOTEA_PCI_LOWER_MEM 0x80000000 +#define OCOTEA_PCI_UPPER_MEM 0xffffefff + +#define OCOTEA_PCI_CFGREGS_BASE 0x000000020ec00000ULL +#define OCOTEA_PCI_CFGA_PLB32 0x0ec00000 +#define OCOTEA_PCI_CFGD_PLB32 0x0ec00004 + +#define OCOTEA_PCI_IO_BASE 0x0000000208000000ULL +#define OCOTEA_PCI_IO_SIZE 0x00010000 +#define OCOTEA_PCI_MEM_OFFSET 0x00000000 + +#endif /* __ASM_OCOTEA_H__ */ +#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/platforms/walnut.c cset-v2.4.20/arch/ppc/platforms/walnut.c --- cset-v2.4.20~/arch/ppc/platforms/walnut.c 2004-10-25 15:03:47.000000000 +0900 +++ cset-v2.4.20/arch/ppc/platforms/walnut.c 2004-11-01 22:35:10.000000000 +0900 @@ -5,16 +5,27 @@ * * Copyright (c) 1999-2000 Grant Erickson * - * Module name: walnut_setup.c + * Copyright 2000-2002 MontaVista Software Inc. + * Completed implementation. + * Author: MontaVista Software, Inc. + * + * Module name: walnut.c * * Description: * Architecture- / platform-specific boot-time initialization code for - * the IBM PowerPC 403GP "Walnut" evaluation board. Adapted from original + * IBM PowerPC 4xx based boards. Adapted from original * code by Gary Thomas, Cort Dougan , and Dan Malek * . * + * History: 11/09/2001 - armin + * added board_init to add in additional instuctions needed during platfrom_init + * + * 01/22/2002 - Armin + * converted pci to ocp + * + * + * Please read the COPYING file for all license details. */ - #include #include #include @@ -19,273 +30,227 @@ #include #include #include -#include #include #include #include -#include +#include +#include +#include +#include #include -#include #include #include - -#include "ppc4xx_pic.h" #include -#include "walnut_setup.h" - - -/* Function Prototypes */ - -extern void abort(void); - -/* Global Variables */ - -unsigned char __res[sizeof(bd_t)]; - - -/* - * void __init walnut_init() - * - * Description: - * This routine... - * - * Input(s): - * r3 - Optional pointer to a board information structure. - * r4 - Optional pointer to the physical starting address of the init RAM - * disk. - * r5 - Optional pointer to the physical ending address of the init RAM - * disk. - * r6 - Optional pointer to the physical starting address of any kernel - * command-line parameters. - * r7 - Optional pointer to the physical ending address of any kernel - * command-line parameters. - * - * Output(s): - * N/A - * - * Returns: - * N/A - * - */ -void __init -walnut_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - /* - * If we were passed in a board information, copy it into the - * residual data area. - */ - if (r3) { - memcpy((void *)__res, (void *)(r3 + KERNELBASE), sizeof(bd_t)); - } - -#if defined(CONFIG_BLK_DEV_INITRD) - /* - * If the init RAM disk has been configured in, and there's a valid - * starting address for it, set it up. - */ - if (r4) { - initrd_start = r4 + KERNELBASE; - initrd_end = r5 + KERNELBASE; - } -#endif /* CONFIG_BLK_DEV_INITRD */ - - /* Copy the kernel command line arguments to a safe place. */ - - if (r6) { - *(char *)(r7 + KERNELBASE) = 0; - strcpy(cmd_line, (char *)(r6 + KERNELBASE)); - } - - /* Initialize machine-dependency vectors */ - - ppc_md.setup_arch = walnut_setup_arch; - ppc_md.show_percpuinfo = walnut_show_percpuinfo; - ppc_md.irq_cannonicalize = NULL; - ppc_md.init_IRQ = walnut_init_IRQ; - ppc_md.get_irq = walnut_get_irq; - ppc_md.init = NULL; - - ppc_md.restart = walnut_restart; - ppc_md.power_off = walnut_power_off; - ppc_md.halt = walnut_halt; - - ppc_md.time_init = walnut_time_init; - ppc_md.set_rtc_time = walnut_set_rtc_time; - ppc_md.get_rtc_time = walnut_get_rtc_time; - ppc_md.calibrate_decr = walnut_calibrate_decr; - - ppc_md.kbd_setkeycode = NULL; - ppc_md.kbd_getkeycode = NULL; - ppc_md.kbd_translate = NULL; - ppc_md.kbd_unexpected_up = NULL; - ppc_md.kbd_leds = NULL; - ppc_md.kbd_init_hw = NULL; - ppc_md.ppc_kbd_sysrq_xlate = NULL; -} +#include +#include +#include + +#undef DEBUG + +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +void *kb_cs; +void *kb_data; +void *walnut_rtc_base; -/* - * Document me. +/* Some IRQs unique to Walnut. + * Used by the generic 405 PCI setup functions in ppc4xx_pci.c */ -void __init -walnut_setup_arch(void) +int __init +ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) { - /* XXX - Implement me */ -} - + static char pci_irq_table[][4] = /* - * int walnut_show_percpuinfo() - * - * Description: - * This routine pretty-prints the platform's internal CPU and bus clock - * frequencies into the buffer for usage in /proc/cpuinfo. - * - * Input(s): - * *buffer - Buffer into which CPU and bus clock frequencies are to be - * printed. - * - * Output(s): - * *buffer - Buffer with the CPU and bus clock frequencies. - * - * Returns: - * The number of bytes copied into 'buffer' if OK, otherwise zero or less - * on error. + * PCI IDSEL/INTPIN->INTLINE + * A B C D */ -int -walnut_show_percpuinfo(struct seq_file *m) { - bd_t *bp = (bd_t *)__res; - - seq_printf(m, "clock\t\t: %dMHz\n" - "bus clock\t\t: %dMHz\n", - bp->bi_intfreq / 1000000, - bp->bi_busfreq / 1000000); + {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */ + {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */ + {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */ + {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */ + }; - return 0; -} + const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; + return PCI_IRQ_TABLE_LOOKUP; +}; -/* - * Document me. - */ void __init -walnut_init_IRQ(void) +board_setup_arch(void) { - int i; - - ppc4xx_pic_init(); +#define WALNUT_PS2_BASE 0xF0100000 +#define WALNUT_FPGA_BASE 0xF0300000 - for (i = 0; i < NR_IRQS; i++) { - irq_desc[i].handler = ppc4xx_pic; + void *fpga_brdc; + unsigned char fpga_brdc_data; + void *fpga_enable; + void *fpga_polarity; + void *fpga_status; + void *fpga_trigger; + + kb_data = ioremap(WALNUT_PS2_BASE, 8); + if (!kb_data) { + printk(KERN_CRIT + "walnut_setup_arch() kb_data ioremap failed\n"); + return; } + kb_cs = kb_data + 1; + + fpga_status = ioremap(WALNUT_FPGA_BASE, 8); + if (!fpga_status) { + printk(KERN_CRIT + "walnut_setup_arch() fpga_status ioremap failed\n"); return; } -/* - * Document me. - */ -int -walnut_get_irq(struct pt_regs *regs) -{ - return (ppc4xx_pic_get_irq(regs)); + fpga_enable = fpga_status + 1; + fpga_polarity = fpga_status + 2; + fpga_trigger = fpga_status + 3; + fpga_brdc = fpga_status + 4; + + /* split the keyboard and mouse interrupts */ + fpga_brdc_data = readb(fpga_brdc); + fpga_brdc_data |= 0x80; + writeb(fpga_brdc_data, fpga_brdc); + + writeb(0x3, fpga_enable); + + writeb(0x3, fpga_polarity); + + writeb(0x3, fpga_trigger); + + /* RTC step for the walnut */ + walnut_rtc_base = (void *) WALNUT_RTC_VADDR; + TODC_INIT(TODC_TYPE_DS1743, walnut_rtc_base, walnut_rtc_base, + walnut_rtc_base, 8); + /* Identify the system */ + printk("IBM Walnut port (C) 2000-2002 MontaVista Software, Inc. (source@mvista.com)\n"); } -/* - * Document me. - */ -void -walnut_restart(char *cmd) +void __init +bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip) { - abort(); -} + unsigned int bar_response, bar; /* - * Document me. + * Expected PCI mapping: + * + * PLB addr PCI memory addr + * --------------------- --------------------- + * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff + * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff + * + * PLB addr PCI io addr + * --------------------- --------------------- + * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000 + * + * The following code is simplified by assuming that the bootrom + * has been well behaved in following this mapping. */ -void -walnut_power_off(void) -{ - walnut_restart(NULL); -} -/* - * Document me. - */ -void -walnut_halt(void) -{ - walnut_restart(NULL); -} +#ifdef DEBUG + int i; -/* - * Document me. - */ -long __init -walnut_time_init(void) -{ - /* XXX - Implement me */ - return 0; + printk("ioremap PCLIO_BASE = 0x%x\n", pcip); + printk("PCI bridge regs before fixup \n"); + for (i = 0; i <= 3; i++) { + printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); + printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); + printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila))); + printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha))); + } + printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); + printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); + printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); + printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); + +#endif + + /* added for IBM boot rom version 1.15 bios bar changes -AK */ + + /* Disable region first */ + out_le32((void *) &(pcip->pmm[0].ma), 0x00000000); + /* PLB starting addr, PCI: 0x80000000 */ + out_le32((void *) &(pcip->pmm[0].la), 0x80000000); + /* PCI start addr, 0x80000000 */ + out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE); + /* 512MB range of PLB to PCI */ + out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000); + /* Enable no pre-fetch, enable region */ + out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff - + (PPC405_PCI_UPPER_MEM - + PPC405_PCI_MEM_BASE)) | 0x01)); + + /* Disable region one */ + out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); + out_le32((void *) &(pcip->pmm[1].la), 0x00000000); + out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000); + out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000); + out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); + out_le32((void *) &(pcip->ptm1ms), 0x00000000); + + /* Disable region two */ + out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); + out_le32((void *) &(pcip->pmm[2].la), 0x00000000); + out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000); + out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000); + out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); + out_le32((void *) &(pcip->ptm2ms), 0x00000000); + + /* Zero config bars */ + for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { + early_write_config_dword(hose, hose->first_busno, + PCI_FUNC(hose->first_busno), bar, + 0x00000000); + early_read_config_dword(hose, hose->first_busno, + PCI_FUNC(hose->first_busno), bar, + &bar_response); + DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n", + hose->first_busno, PCI_SLOT(hose->first_busno), + PCI_FUNC(hose->first_busno), bar, bar_response); + } + /* end work arround */ + +#ifdef DEBUG + printk("PCI bridge regs after fixup \n"); + for (i = 0; i <= 3; i++) { + printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); + printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); + printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila))); + printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha))); + } + printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); + printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); + printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); + printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); + +#endif } -/* - * Document me. - */ -int __init -walnut_set_rtc_time(unsigned long time) +void __init +board_io_mapping(void) { - /* XXX - Implement me */ - - return (0); + io_block_mapping(WALNUT_RTC_VADDR, + WALNUT_RTC_PADDR, WALNUT_RTC_SIZE, _PAGE_IO); } -/* - * Document me. - */ -unsigned long __init -walnut_get_rtc_time(void) +void __init +board_setup_irq(void) { - /* XXX - Implement me */ - - return (0); } -/* - * void __init walnut_calibrate_decr() - * - * Description: - * This routine retrieves the internal processor frequency from the board - * information structure, sets up the kernel timer decrementer based on - * that value, enables the 403 programmable interval timer (PIT) and sets - * it up for auto-reload. - * - * Input(s): - * N/A - * - * Output(s): - * N/A - * - * Returns: - * N/A - * - */ void __init -walnut_calibrate_decr(void) +board_init(void) { - unsigned int freq; - bd_t *bip = (bd_t *)__res; - - freq = bip->bi_intfreq; - - decrementer_count = freq / HZ; - count_period_num = 1; - count_period_den = freq; - - /* Enable the PIT and set auto-reload of its value */ - - mtspr(SPRN_TCR, TCR_PIE | TCR_ARE); - - /* Clear any pending timer interrupts */ - - mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_PIS | TSR_FIS); + ppc_md.time_init = todc_time_init; + ppc_md.set_rtc_time = todc_set_rtc_time; + ppc_md.get_rtc_time = todc_get_rtc_time; + ppc_md.nvram_read_val = todc_direct_read_val; + ppc_md.nvram_write_val = todc_direct_write_val; } diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/arch/ppc/platforms/walnut.h cset-v2.4.20/arch/ppc/platforms/walnut.h --- cset-v2.4.20~/arch/ppc/platforms/walnut.h 2004-10-25 14:59:25.000000000 +0900 +++ cset-v2.4.20/arch/ppc/platforms/walnut.h 2004-11-01 22:35:10.000000000 +0900 @@ -3,51 +3,92 @@ */ /* * - * Copyright (c) 1999-2000 Grant Erickson + * Copyright (c) 1999 Grant Erickson * - * Module name: walnut_setup.c + * Copyright 2000 MontaVista Software Inc. + * PPC405 modifications + * Author: MontaVista Software, Inc. + * frank_rowand@mvista.com or source@mvista.com + * debbie_chu@mvista.com + * + * Module name: ppc405.h * * Description: - * Architecture- / platform-specific boot-time initialization code for - * the IBM PowerPC 405GP "Walnut" evaluation board. Adapted from original - * code by Gary Thomas, Cort Dougan , and Dan Malek - * . + * Macros, definitions, and data structures specific to the IBM PowerPC + * based boards. + * + * This includes: + * + * 405GP "Walnut" evaluation board * + * Please read the COPYING file for all license details. */ -#ifndef __WALNUT_SETUP_H__ -#define __WALNUT_SETUP_H__ +#ifdef __KERNEL__ +#ifndef __ASM_WALNUT_H__ +#define __ASM_WALNUT_H__ -#include -#include +/* We have a 405GP core */ +#include +#ifndef __ASSEMBLY__ +/* + * Data structure defining board information maintained by the boot + * ROM on IBM's "Walnut" evaluation board. An effort has been made to + * keep the field names consistent with the 8xx 'bd_t' board info + * structures. + */ -#ifdef __cplusplus -extern "C" { -#endif +typedef struct board_info { + unsigned char bi_s_version[4]; /* Version of this structure */ + unsigned char bi_r_version[30]; /* Version of the IBM ROM */ + unsigned int bi_memsize; /* DRAM installed, in bytes */ + unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */ + unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ + unsigned int bi_intfreq; /* Processor speed, in Hz */ + unsigned int bi_busfreq; /* PLB Bus speed, in Hz */ + unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ + unsigned int bi_opbfreq; /* OPB Bus speed, in Hz */ + int bi_iic_fast[1]; /* Use fast i2c mode */ +} bd_t; -extern unsigned char __res[sizeof(bd_t)]; +/* Some 4xx parts use a different timebase frequency from the internal clock. +*/ +#define bi_tbfreq bi_intfreq -extern void walnut_init(unsigned long r3, - unsigned long ird_start, - unsigned long ird_end, - unsigned long cline_start, - unsigned long cline_end); -extern void walnut_setup_arch(void); -extern int walnut_setup_residual(char *buffer); -extern void walnut_init_IRQ(void); -extern int walnut_get_irq(struct pt_regs *regs); -extern void walnut_restart(char *cmd); -extern void walnut_power_off(void); -extern void walnut_halt(void); -extern void walnut_time_init(void); -extern int walnut_set_rtc_time(unsigned long now); -extern unsigned long walnut_get_rtc_time(void); -extern void walnut_calibrate_decr(void); +/* Memory map for the IBM "Walnut" 405GP evaluation board. + * Generic 4xx plus RTC. + */ -#ifdef __cplusplus -} +extern void *walnut_rtc_base; +#define WALNUT_RTC_PADDR ((uint)0xf0000000) +#define WALNUT_RTC_VADDR WALNUT_RTC_PADDR +#define WALNUT_RTC_SIZE ((uint)8*1024) + +/* ps2 keyboard and mouse */ +#define KEYBOARD_IRQ 25 +#define AUX_IRQ 26 + +#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK +#define BASE_BAUD 201600 +#else +#define BASE_BAUD 691200 #endif -#endif /* __WALNUT_SETUP_H__ */ +#define WALNUT_PS2_BASE 0xF0100000 +#define WALNUT_FPGA_BASE 0xF0300000 + + +extern void *kb_cs; +extern void *kb_data; +#define kbd_read_input() readb(kb_data) +#define kbd_read_status() readb(kb_cs) +#define kbd_write_output(val) writeb(val, kb_data) +#define kbd_write_command(val) writeb(val, kb_cs) + +#define PPC4xx_MACHINE_NAME "IBM Walnut" + +#endif /* !__ASSEMBLY__ */ +#endif /* __ASM_WALNUT_H__ */ +#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/drivers/net/Config.in cset-v2.4.20/drivers/net/Config.in --- cset-v2.4.20~/drivers/net/Config.in 2004-10-25 14:59:31.000000000 +0900 +++ cset-v2.4.20/drivers/net/Config.in 2004-11-01 22:35:10.000000000 +0900 @@ -257,6 +257,10 @@ dep_tristate 'iSeries Virtual Ethernet driver support' CONFIG_VETH $CONFIG_PPC_ISERIES fi +if [ "$CONFIG_4xx" = "y" ]; then + source drivers/net/ibm_emac/Config.in +fi + bool 'FDDI driver support' CONFIG_FDDI if [ "$CONFIG_FDDI" = "y" ]; then if [ "$CONFIG_PCI" = "y" -o "$CONFIG_EISA" = "y" ]; then diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/drivers/net/Makefile cset-v2.4.20/drivers/net/Makefile --- cset-v2.4.20~/drivers/net/Makefile 2004-10-25 15:02:01.000000000 +0900 +++ cset-v2.4.20/drivers/net/Makefile 2004-11-01 22:35:10.000000000 +0900 @@ -25,6 +25,8 @@ obj-y += tulip/tulip.o endif +obj-$(CONFIG_OCP_NET) += ibm_emac/ocp.o + ifeq ($(CONFIG_E1000),y) obj-y += e1000/e1000.o endif @@ -36,6 +38,7 @@ subdir-$(CONFIG_NET_PCMCIA) += pcmcia subdir-$(CONFIG_NET_WIRELESS) += wireless subdir-$(CONFIG_TULIP) += tulip +subdir-$(CONFIG_OCP_NET) += ibm_emac subdir-$(CONFIG_IRDA) += irda subdir-$(CONFIG_TR) += tokenring subdir-$(CONFIG_WAN) += wan diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/drivers/net/ibm_emac/Config.in cset-v2.4.20/drivers/net/ibm_emac/Config.in --- cset-v2.4.20~/drivers/net/ibm_emac/Config.in 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/drivers/net/ibm_emac/Config.in 2004-11-01 22:35:10.000000000 +0900 @@ -0,0 +1,24 @@ +# +# On-chip network configuration +# +mainmenu_option next_comment +comment 'On-chip net devices' +if [ "$CONFIG_IBM_OCP" = "y" ]; then + bool ' IBM on-chip ethernet' CONFIG_IBM_OCP_ENET + if [ "$CONFIG_IBM_OCP_ENET" = "y" ]; then + bool ' Verbose error messages' CONFIG_IBM_OCP_ENET_ERROR_MSG + int ' Number of receive buffers' CONFIG_IBM_OCP_ENET_RX_BUFF 64 + int ' Number of transmit buffers' CONFIG_IBM_OCP_ENET_TX_BUFF 8 + int ' Frame gap' CONFIG_IBM_OCP_ENET_GAP 8 + int ' Skb reserve amount' CONFIG_IBM_OCP_ENET_SKB_RES 0 + fi + if [ "$CONFIG_IBM_OCP_ENET" = "y" ]; then + define_bool CONFIG_OCP_NET y + if [ "$CONFIG_NP405H" = "y" -o "$CONFIG_NP405L" = "y" \ + -o "$CONFIG_440" = "y" ]; then + define_int CONFIG_IBM_OCP_MAL_CNT 1 + define_bool CONFIG_IBM_OCP_ZMII y + fi + fi +fi +endmenu diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/drivers/net/ibm_emac/Makefile cset-v2.4.20/drivers/net/ibm_emac/Makefile --- cset-v2.4.20~/drivers/net/ibm_emac/Makefile 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/drivers/net/ibm_emac/Makefile 2004-11-01 22:35:10.000000000 +0900 @@ -0,0 +1,26 @@ +# +# Makefile for the On-chip ethernet drivers +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# +# Note 2! The CFLAGS definitions are now in the main makefile... + + +obj-y := +obj-m := + +O_TARGET := ocp.o + +# Module support doesn't work yet. +export-objs := + +obj-$(CONFIG_IBM_OCP_ENET) += ibm_ocp_enet.o ibm_ocp_phy.o ibm_ocp_mal.o + +# Only need this if you want to see additional debug messages +ifeq ($(CONFIG_IBM_OCP_ENET_ERROR_MSG), y) +obj-$(CONFIG_IBM_OCP_ENET) += ibm_ocp_debug.o +endif + +include $(TOPDIR)/Rules.make diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/drivers/net/ibm_emac/ibm_emac.h cset-v2.4.20/drivers/net/ibm_emac/ibm_emac.h --- cset-v2.4.20~/drivers/net/ibm_emac/ibm_emac.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/drivers/net/ibm_emac/ibm_emac.h 2004-11-02 12:57:39.000000000 +0900 @@ -0,0 +1,262 @@ +/* + * ibm_emac.h + * + * + * Armin Kuster akuster@mvista.com + * June, 2002 + * + * Copyright 2002 MontaVista Softare Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Version: 1.0: 06/02/02 - armin + * pulled all emac defined out od enet.h + * + */ + +#ifndef _IBM_OCP_EMAC_H_ +#define _IBM_OCP_EMAC_H_ +/* General defines needed for the driver */ + +/* Emac */ +typedef struct emac_regs { + u32 em0mr0; + u32 em0mr1; + u32 em0tmr0; + u32 em0tmr1; + u32 em0rmr; + u32 em0isr; + u32 em0iser; + u32 em0iahr; + u32 em0ialr; + u32 em0vtpid; + u32 em0vtci; + u32 em0ptr; + u32 em0iaht1; + u32 em0iaht2; + u32 em0iaht3; + u32 em0iaht4; + u32 em0gaht1; + u32 em0gaht2; + u32 em0gaht3; + u32 em0gaht4; + u32 em0lsah; + u32 em0lsal; + u32 em0ipgvr; + u32 em0stacr; + u32 em0trtr; + u32 em0rwmr; +} emac_t; + + +/* MODE REG 0 */ +#define EMAC_M0_RXI 0x80000000 +#define EMAC_M0_TXI 0x40000000 +#define EMAC_M0_SRST 0x20000000 +#define EMAC_M0_TXE 0x10000000 +#define EMAC_M0_RXE 0x08000000 +#define EMAC_M0_WKE 0x04000000 + +/* MODE Reg 1 */ +#define EMAC_M1_FDE 0x80000000 +#define EMAC_M1_ILE 0x40000000 +#define EMAC_M1_VLE 0x20000000 +#define EMAC_M1_EIFC 0x10000000 +#define EMAC_M1_APP 0x08000000 +#define EMAC_M1_AEMI 0x02000000 +#define EMAC_M1_IST 0x01000000 +#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */ +#define EMAC_M1_MF_100MBPS 0x00400000 +#define EMAC_M1_TR 0x00008000 +#ifdef CONFIG_IBM_EMAC4 +#define EMAC_M1_RFS_16K 0x00280000 /* 000 for 512 byte */ +#define EMAC_M1_RFS_8K 0x00200000 +#define EMAC_M1_RFS_4K 0x00180000 +#define EMAC_M1_RFS_2K 0x00100000 +#define EMAC_M1_RFS_1K 0x00080000 +#define EMAC_M1_TX_FIFO_16K 0x00050000 /* 0's for 512 byte */ +#define EMAC_M1_TX_FIFO_8K 0x00040000 +#define EMAC_M1_TX_FIFO_4K 0x00030000 +#define EMAC_M1_TX_FIFO_2K 0x00020000 +#define EMAC_M1_TX_FIFO_1K 0x00010000 +#define EMAC_M1_TX_MWSW 0x00001000 /* 0 wait for status */ +#define EMAC_M1_JUMBO_ENABLE 0x00000800 /* Upt to 9Kr status */ +#define EMAC_M1_OPB_CLK_66 0x00000008 /* 66Mhz */ +#define EMAC_M1_OPB_CLK_83 0x00000010 /* 83Mhz */ +#define EMAC_M1_OPB_CLK_100 0x00000018 /* 100Mhz */ +#define EMAC_M1_OPB_CLK_100P 0x00000020 /* 100Mhz+ */ +#else /* CONFIG_IBM_EMAC4 */ +#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */ +#define EMAC_M1_RFS_2K 0x00200000 +#define EMAC_M1_RFS_1K 0x00100000 +#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */ +#define EMAC_M1_TX_FIFO_1K 0x00040000 +#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */ +#define EMAC_M1_TR1_DEPEND 0x00004000 +#define EMAC_M1_TR1_MULTI 0x00002000 +#define EMAC_M1_JUMBO_ENABLE 0x00001000 +#endif /* CONFIG_IBM_EMAC4 */ +#define EMAC_M1_BASE (EMAC_M1_RFS_4K | \ + EMAC_M1_TX_FIFO_2K | \ + EMAC_M1_APP | \ + EMAC_M1_TR) + +/* Transmit Mode Register 0 */ +#define EMAC_TMR0_GNP0 0x80000000 +#define EMAC_TMR0_GNP1 0x40000000 +#define EMAC_TMR0_GNPD 0x20000000 +#define EMAC_TMR0_FC 0x10000000 +#define EMAC_TMR0_TFAE_2_32 0x00000001 +#define EMAC_TMR0_TFAE_4_64 0x00000002 +#define EMAC_TMR0_TFAE_8_128 0x00000003 +#define EMAC_TMR0_TFAE_16_256 0x00000004 +#define EMAC_TMR0_TFAE_32_512 0x00000005 +#define EMAC_TMR0_TFAE_64_1024 0x00000006 +#define EMAC_TMR0_TFAE_128_2048 0x00000007 + +/* Receive Mode Register */ +#define EMAC_RMR_SP 0x80000000 +#define EMAC_RMR_SFCS 0x40000000 +#define EMAC_RMR_ARRP 0x20000000 +#define EMAC_RMR_ARP 0x10000000 +#define EMAC_RMR_AROP 0x08000000 +#define EMAC_RMR_ARPI 0x04000000 +#define EMAC_RMR_PPP 0x02000000 +#define EMAC_RMR_PME 0x01000000 +#define EMAC_RMR_PMME 0x00800000 +#define EMAC_RMR_IAE 0x00400000 +#define EMAC_RMR_MIAE 0x00200000 +#define EMAC_RMR_BAE 0x00100000 +#define EMAC_RMR_MAE 0x00080000 +#define EMAC_RMR_RFAF_2_32 0x00000001 +#define EMAC_RMR_RFAF_4_64 0x00000002 +#define EMAC_RMR_RFAF_8_128 0x00000003 +#define EMAC_RMR_RFAF_16_256 0x00000004 +#define EMAC_RMR_RFAF_32_512 0x00000005 +#define EMAC_RMR_RFAF_64_1024 0x00000006 +#define EMAC_RMR_RFAF_128_2048 0x00000007 +#define EMAC_RMR_BASE (EMAC_RMR_IAE | EMAC_RMR_BAE) + +/* Interrupt Status & enable Regs */ +#define EMAC_ISR_OVR 0x02000000 +#define EMAC_ISR_PP 0x01000000 +#define EMAC_ISR_BP 0x00800000 +#define EMAC_ISR_RP 0x00400000 +#define EMAC_ISR_SE 0x00200000 +#define EMAC_ISR_ALE 0x00100000 +#define EMAC_ISR_BFCS 0x00080000 +#define EMAC_ISR_PTLE 0x00040000 +#define EMAC_ISR_ORE 0x00020000 +#define EMAC_ISR_IRE 0x00010000 +#define EMAC_ISR_DBDM 0x00000200 +#define EMAC_ISR_DB0 0x00000100 +#define EMAC_ISR_SE0 0x00000080 +#define EMAC_ISR_TE0 0x00000040 +#define EMAC_ISR_DB1 0x00000020 +#define EMAC_ISR_SE1 0x00000010 +#define EMAC_ISR_TE1 0x00000008 +#define EMAC_ISR_MOS 0x00000002 +#define EMAC_ISR_MOF 0x00000001 + +/* STA CONTROL REG */ +#define EMAC_STACR_OC 0x00008000 +#define EMAC_STACR_PHYE 0x00004000 +#define EMAC_STACR_WRITE 0x00002000 +#define EMAC_STACR_READ 0x00001000 +#define EMAC_STACR_CLK_83MHZ 0x00000800 /* 0's for 50Mhz */ +#define EMAC_STACR_CLK_66MHZ 0x00000400 +#define EMAC_STACR_CLK_100MHZ 0x00000C00 + +/* Transmit Request Threshold Register */ +#define EMAC_TRTR_1600 0x18000000 /* 0's for 64 Bytes */ +#define EMAC_TRTR_256 0x03000000 +#define EMAC_TRTR_192 0x10000000 +#define EMAC_TRTR_128 0x01000000 + +#define EMAC_TX_CTRL_GFCS 0x0200 +#define EMAC_TX_CTRL_GP 0x0100 +#define EMAC_TX_CTRL_ISA 0x0080 +#define EMAC_TX_CTRL_RSA 0x0040 +#define EMAC_TX_CTRL_IVT 0x0020 +#define EMAC_TX_CTRL_RVT 0x0010 + +#define EMAC_TX_CTRL_DFLT ( \ + MAL_TX_CTRL_LAST | MAL_TX_CTRL_READY | MAL_TX_CTRL_INTR | \ + EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP ) + +/* madmal transmit status / Control bits */ +#define EMAC_TX_ST_BFCS 0x0200 +#define EMAC_TX_ST_BPP 0x0100 +#define EMAC_TX_ST_LCS 0x0080 +#define EMAC_TX_ST_ED 0x0040 +#define EMAC_TX_ST_EC 0x0020 +#define EMAC_TX_ST_LC 0x0010 +#define EMAC_TX_ST_MC 0x0008 +#define EMAC_TX_ST_SC 0x0004 +#define EMAC_TX_ST_UR 0x0002 +#define EMAC_TX_ST_SQE 0x0001 + +/* madmal receive status / Control bits */ +#define EMAC_RX_ST_OE 0x0200 +#define EMAC_RX_ST_PP 0x0100 +#define EMAC_RX_ST_BP 0x0080 +#define EMAC_RX_ST_RP 0x0040 +#define EMAC_RX_ST_SE 0x0020 +#define EMAC_RX_ST_AE 0x0010 +#define EMAC_RX_ST_BFCS 0x0008 +#define EMAC_RX_ST_PTL 0x0004 +#define EMAC_RX_ST_ORE 0x0002 +#define EMAC_RX_ST_IRE 0x0001 +#define EMAC_BAD_RX_PACKET 0x02ff + +/* Revision specific EMAC register defaults */ +#ifdef CONFIG_IBM_EMAC4 +#define EMAC_M1_DEFAULT (EMAC_M1_BASE | \ + EMAC_M1_OPB_CLK_66 | \ + EMAC_M1_TX_MWSW) +#define EMAC_RMR_DEFAULT (EMAC_RMR_BASE | \ + EMAC_RMR_RFAF_128_2048) +#define EMAC_TMR0_XMIT (EMAC_TMR0_GNP0 | \ + EMAC_TMR0_TFAE_128_2048) +#define EMAC_TRTR_DEFAULT EMAC_TRTR_256 +#else /* !CONFIG_IBM_EMAC4 */ +#define EMAC_M1_DEFAULT EMAC_M1_BASE +#define EMAC_RMR_DEFAULT EMAC_RMR_BASE +#define EMAC_TMR0_XMIT EMAC_TMR0_GNP0 +#define EMAC_TRTR_DEFAULT EMAC_TRTR_1600 +#endif /* CONFIG_IBM_EMAC4 */ + +/* SoC implementation specific EMAC register defaults */ +#if defined(CONFIG_440GP) +#define EMAC_RWMR_DEFAULT 0x80009000 +#define EMAC_TMR0_DEFAULT 0x00000000 +#define EMAC_TMR1_DEFAULT 0xf8640000 +#elif defined(CONFIG_440GX) +#define EMAC_RWMR_DEFAULT 0x1000a200 +#define EMAC_TMR0_DEFAULT EMAC_TMR0_TFAE_128_2048 +#define EMAC_TMR1_DEFAULT 0x88810000 +#else +#define EMAC_RWMR_DEFAULT 0x0f002000 +#define EMAC_TMR0_DEFAULT 0x00000000 +#define EMAC_TMR1_DEFAULT 0x380f0000 +#endif /* CONFIG_440GP */ + +#endif diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_debug.c cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_debug.c --- cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_debug.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_debug.c 2004-11-01 22:35:10.000000000 +0900 @@ -0,0 +1,264 @@ +/* + * ibm_ocp_debug.c + * + * This has all the debug routines that where in *_enet.c + * + * Armin Kuster akuster@mvista.com + * April , 2002 + * + * Copyright 2002 MontaVista Softare Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * TODO: + * + * Version 1.0: (04/15/02) + * initial release + * These are all the debug routines from *_enet.c and a few new ones. + * this was done to reduce the *_enet.c code. + * + * Version 1.1: 04/24/02 + * fixed missind EMAC_DEV macros - Todd + * + */ + +#include +#include +#include +#include +#include "ibm_ocp_mal.h" +#include "ibm_ocp_zmii.h" +#include "ibm_ocp_enet.h" + +extern int +emac_phy_read(struct net_device *dev, int mii_id, int reg); + +void emac_phy_dump(struct net_device *dev) +{ + struct ocp_enet_private *fep = dev->priv; + unsigned long i; + uint data; + + printk(KERN_DEBUG " Prepare for Phy dump....\n"); + for (i = 0; i < 0x1A; i++) { + data = emac_phy_read(dev, fep->mii_phy_addr, i); + printk(KERN_DEBUG "Phy reg 0x%lx ==> %4x\n", i, data); + if (i == 0x07) + i = 0x0f; + } +} + +void +emac_desc_dump(struct net_device *dev) +{ + struct ocp_enet_private *fep = dev->priv; + int curr_slot; + + printk(KERN_DEBUG "dumping the receive descriptors: current slot is %d\n", + fep->rx_slot); + for (curr_slot = 0; curr_slot < NUM_RX_BUFF; curr_slot++) { + printk(KERN_DEBUG "Desc %02d: status 0x%04x, length %3d, addr 0x%x\n", + curr_slot, + fep->rx_desc[curr_slot].ctrl, + fep->rx_desc[curr_slot].data_len, + (unsigned int) fep->rx_desc[curr_slot].data_ptr); + } +} + +void +emac_mac_dump(struct net_device *dev) +{ + struct ocp_enet_private *fep = dev->priv; + volatile emac_t *emacp = fep->emacp; + + printk(KERN_DEBUG "EMAC DEBUG ********** \n"); + printk(KERN_DEBUG "EMAC_M0 ==> 0x%x\n", in_be32(&emacp->em0mr0)); + printk(KERN_DEBUG "EMAC_M1 ==> 0x%x\n", in_be32(&emacp->em0mr1)); + printk(KERN_DEBUG "EMAC_TXM0==> 0x%x\n", in_be32(&emacp->em0tmr0)); + printk(KERN_DEBUG "EMAC_TXM1==> 0x%x\n", in_be32(&emacp->em0tmr1)); + printk(KERN_DEBUG "EMAC_RXM ==> 0x%x\n", in_be32(&emacp->em0rmr)); + printk(KERN_DEBUG "EMAC_ISR ==> 0x%x\n", in_be32(&emacp->em0isr)); + printk(KERN_DEBUG "EMAC_IER ==> 0x%x\n", in_be32(&emacp->em0iser)); + printk(KERN_DEBUG "EMAC_IAH ==> 0x%x\n", in_be32(&emacp->em0iahr)); + printk(KERN_DEBUG "EMAC_IAL ==> 0x%x\n", in_be32(&emacp->em0ialr)); + printk(KERN_DEBUG "EMAC_VLAN_TPID_REG ==> 0x%x\n", in_be32(&emacp->em0vtpid)); +} + +void +emac_mal_dump(struct net_device *dev) +{ + struct ibm_ocp_mal* mal = ((struct ocp_enet_private*)dev->priv)->mal; + + printk(KERN_DEBUG " MAL DEBUG ********** \n"); + printk(KERN_DEBUG " MCR ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALCR)); + printk(KERN_DEBUG " ESR ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALESR)); + printk(KERN_DEBUG " IER ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALIER)); +#ifdef CONFIG_40x + printk(KERN_DEBUG " DBR ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALDBR)); +#endif /* CONFIG_40x */ + printk(KERN_DEBUG " TXCASR ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALTXCASR)); + printk(KERN_DEBUG " TXCARR ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALTXCARR)); + printk(KERN_DEBUG " TXEOBISR ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALTXEOBISR)); + printk(KERN_DEBUG " TXDEIR ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALTXDEIR)); + printk(KERN_DEBUG " RXCASR ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALRXCASR)); + printk(KERN_DEBUG " RXCARR ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALRXCARR)); + printk(KERN_DEBUG " RXEOBISR ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALRXEOBISR)); + printk(KERN_DEBUG " RXDEIR ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALRXDEIR)); + printk(KERN_DEBUG " TXCTP0R ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALTXCTP0R)); + printk(KERN_DEBUG " TXCTP1R ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALTXCTP1R)); + printk(KERN_DEBUG " TXCTP2R ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALTXCTP2R)); + printk(KERN_DEBUG " TXCTP3R ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALTXCTP3R)); + printk(KERN_DEBUG " RXCTP0R ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALRXCTP0R)); + printk(KERN_DEBUG " RXCTP1R ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALRXCTP1R)); + printk(KERN_DEBUG " RCBS0 ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALRCBS0)); + printk(KERN_DEBUG " RCBS1 ==> 0x%x\n", + (unsigned int) get_mal_dcrn(mal, DCRN_MALRCBS1)); +} + +void +emac_serr_dump_0(struct net_device *dev) +{ + struct ibm_ocp_mal* mal = ((struct ocp_enet_private*)dev->priv)->mal; + unsigned long int mal_error, plb_error, plb_addr; + + mal_error = get_mal_dcrn(mal, DCRN_MALESR); + printk(KERN_DEBUG "ppc405_eth_serr: %s channel %ld \n", + (mal_error & 0x40000000) ? "Receive" : + "Transmit", (mal_error & 0x3e000000) >> 25); + printk(KERN_DEBUG " ----- latched error -----\n"); + if (mal_error & MALESR_DE) + printk(KERN_DEBUG " DE: descriptor error\n"); + if (mal_error & MALESR_OEN) + printk(KERN_DEBUG + " ONE: OPB non-fullword error\n"); + if (mal_error & MALESR_OTE) + printk(KERN_DEBUG " OTE: OPB timeout error\n"); + if (mal_error & MALESR_OSE) + printk(KERN_DEBUG " OSE: OPB slave error\n"); + + if (mal_error & MALESR_PEIN) { + plb_error = mfdcr(DCRN_PLB0_BESR); + printk(KERN_DEBUG + " PEIN: PLB error, PLB0_BESR is 0x%x\n", + (unsigned int) plb_error); + plb_addr = mfdcr(DCRN_PLB0_BEAR); + printk(KERN_DEBUG + " PEIN: PLB error, PLB0_BEAR is 0x%x\n", + (unsigned int) plb_addr); + } +} + +void +emac_serr_dump_1(struct net_device *dev) +{ + struct ibm_ocp_mal* mal = ((struct ocp_enet_private*)dev->priv)->mal; + int mal_error = get_mal_dcrn(mal, DCRN_MALESR); + + printk(KERN_DEBUG " ----- cumulative errors -----\n"); + if (mal_error & MALESR_DEI) + printk(KERN_DEBUG + " DEI: descriptor error interrupt\n"); + if (mal_error & MALESR_ONEI) + printk(KERN_DEBUG + " OPB non-fullword error interrupt\n"); + if (mal_error & MALESR_OTEI) + printk(KERN_DEBUG + " OTEI: timeout error interrupt\n"); + if (mal_error & MALESR_OSEI) + printk(KERN_DEBUG + " OSEI: slave error interrupt\n"); + if (mal_error & MALESR_PBEI) + printk(KERN_DEBUG + " PBEI: PLB bus error interrupt\n"); +} + +void +emac_err_dump(struct net_device *dev, int em0isr) +{ + printk(KERN_DEBUG "%s: on-chip ethernet error:\n", dev->name); + + if (em0isr & EMAC_ISR_OVR) + printk(KERN_DEBUG " OVR: overrun\n"); + if (em0isr & EMAC_ISR_PP) + printk(KERN_DEBUG " PP: control pause packet\n"); + if (em0isr & EMAC_ISR_BP) + printk(KERN_DEBUG " BP: packet error\n"); + if (em0isr & EMAC_ISR_RP) + printk(KERN_DEBUG " RP: runt packet\n"); + if (em0isr & EMAC_ISR_SE) + printk(KERN_DEBUG " SE: short event\n"); + if (em0isr & EMAC_ISR_ALE) + printk(KERN_DEBUG + " ALE: odd number of nibbles in packet\n"); + if (em0isr & EMAC_ISR_BFCS) + printk(KERN_DEBUG " BFCS: bad FCS\n"); + if (em0isr & EMAC_ISR_PTLE) + printk(KERN_DEBUG " PTLE: oversized packet\n"); + if (em0isr & EMAC_ISR_ORE) + printk(KERN_DEBUG + " ORE: packet length field > max allowed LLC\n"); + if (em0isr & EMAC_ISR_IRE) + printk(KERN_DEBUG " IRE: In Range error\n"); + if (em0isr & EMAC_ISR_DBDM) + printk(KERN_DEBUG " DBDM: xmit error or SQE\n"); + if (em0isr & EMAC_ISR_DB0) + printk(KERN_DEBUG + " DB0: xmit error or SQE on TX channel 0\n"); + if (em0isr & EMAC_ISR_SE0) + printk(KERN_DEBUG + " SE0: Signal Quality Error test failure from TX channel 0\n"); + if (em0isr & EMAC_ISR_TE0) + printk(KERN_DEBUG " TE0: xmit channel 0 aborted\n"); + if (em0isr & EMAC_ISR_DB1) + printk(KERN_DEBUG + " DB1: xmit error or SQE on TX channel \n"); + if (em0isr & EMAC_ISR_SE1) + printk(KERN_DEBUG + " SE1: Signal Quality Error test failure from TX channel 1\n"); + if (em0isr & EMAC_ISR_TE1) + printk(KERN_DEBUG " TE1: xmit channel 1 aborted\n"); + if (em0isr & EMAC_ISR_MOS) + printk(KERN_DEBUG " MOS\n"); + if (em0isr & EMAC_ISR_MOF) + printk(KERN_DEBUG " MOF\n"); + + emac_mac_dump(dev); + emac_mal_dump(dev); +} diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_enet.c cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_enet.c --- cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_enet.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_enet.c 2004-11-02 12:57:39.000000000 +0900 @@ -0,0 +1,1445 @@ +/* + * ibm_ocp_enet.c + * + * Ethernet driver for the built in ethernet on the IBM 4xx PowerPC + * processors. + * + * (c) 2003 Benjamin Herrenschmidt + * + * Based on original work by + * + * Armin Kuster + * Johnnie Peters + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * TODO + * - Check for races in the "remove" code path + * - Add some Power Management to the MAC and the PHY + * - Audit remaining of non-rewritten code (--BenH) + * - Cleanup message display using msglevel mecanism + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "ibm_ocp_enet.h" + +//#define MDIO_DEBUG(fmt) printk fmt +#define MDIO_DEBUG(fmt) + +//#define LINK_DEBUG(fmt) printk fmt +#define LINK_DEBUG(fmt) + +//#define PKT_DEBUG(fmt) printk fmt +#define PKT_DEBUG(fmt) + +#define DRV_NAME "emac" +#define DRV_VERSION "2.0" +#define DRV_AUTHOR "Benjamin Herrenschmidt " +#define DRV_DESC "IBM OCP EMAC Ethernet driver" + +MODULE_AUTHOR(DRV_AUTHOR); +MODULE_DESCRIPTION(DRV_DESC); +MODULE_LICENSE("GPL"); + +static int skb_res = SKB_RES; +MODULE_PARM(skb_res, "i"); +MODULE_PARM_DESC(skb_res, "Amount of data to reserve on skb buffs\n" + "The 405 handles a misaligned IP header fine but\n" + "this can help if you are routing to a tunnel or a\n" + "device that needs aligned data. 0..2"); + +#define ZMII_PRIV(ocpdev) ((struct ibm_ocp_zmii*)ocp_get_drvdata(ocpdev)) + +static unsigned int zmii_enable[][4] = { + {ZMII_SMII0, ZMII_RMII0, ZMII_MII0, + ~(ZMII_MDI1 | ZMII_MDI2 | ZMII_MDI3)}, + {ZMII_SMII1, ZMII_RMII1, ZMII_MII1, + ~(ZMII_MDI0 | ZMII_MDI2 | ZMII_MDI3)}, + {ZMII_SMII2, ZMII_RMII2, ZMII_MII2, + ~(ZMII_MDI0 | ZMII_MDI1 | ZMII_MDI3)}, + {ZMII_SMII3, ZMII_RMII3, ZMII_MII3, ~(ZMII_MDI0 | ZMII_MDI1 | ZMII_MDI2)} +}; +static unsigned int mdi_enable[] = + { ZMII_MDI0, ZMII_MDI1, ZMII_MDI2, ZMII_MDI3 }; + +static unsigned int zmii_speed = 0x0; +static unsigned int zmii_speed100[] = { ZMII_MII0_100MB, ZMII_MII1_100MB }; + +/* Since multiple EMACs share MDIO lines in various ways, we need + * to avoid re-using the same PHY ID in cases where the arch didn't + * setup precise emac_phy_map entries + */ +static u32 busy_phy_map = 0; + +static struct net_device_stats * +emac_stats(struct net_device *dev) +{ + struct ocp_enet_private *fep = dev->priv; + return &fep->stats; +} + +static int +emac_init_zmii(struct ocp_device *ocpdev, int mode) +{ + struct ibm_ocp_zmii *zmii = ZMII_PRIV(ocpdev); + struct zmii_regs *zmiip; + const char *mode_name[] = { "SMII", "RMII", "MII" }; + + if (zmii){ + /* We have already initialized ZMII device, + so just increment refcount and return */ + zmii->users++; + return 0; + } + + zmii = kmalloc(sizeof(struct ibm_ocp_zmii), GFP_KERNEL); + if (zmii == NULL) { + printk(KERN_ERR "zmii%d: Out of memory allocating ZMII structure!\n", + ocpdev->def->index); + return -ENOMEM; + } + memset(zmii, 0, sizeof(*zmii)); + + zmiip = (struct zmii_regs *)ioremap(ocpdev->def->paddr, sizeof(*zmiip)); + if (zmiip == NULL){ + printk(KERN_ERR "zmii%d: Cannot ioremap bridge registers!\n", + ocpdev->def->index); + + kfree(zmii); + return -ENOMEM; + } + + if (mode == ZMII_AUTO) { + if (zmiip->fer & (ZMII_MII0 | ZMII_MII1 | + ZMII_MII2 | ZMII_MII3)) + mode = MII; + if (zmiip->fer & (ZMII_RMII0 | ZMII_RMII1 | + ZMII_RMII2 | ZMII_RMII3)) + mode = RMII; + if (zmiip->fer & (ZMII_SMII0 | ZMII_SMII1 | + ZMII_SMII2 | ZMII_SMII3)) + mode = SMII; + + /* Failsafe: ZMII_AUTO is invalid index into the arrays, + so force SMII if all else fails. */ + + if (mode == ZMII_AUTO) + mode = SMII; + } + + zmii->base = zmiip; + zmii->mode = mode; + zmii->users++; + ocp_set_drvdata(ocpdev, zmii); + + printk(KERN_NOTICE "zmii%d: bridge in %s mode\n", ocpdev->def->index, + mode_name[mode]); + return 0; +} + +static void +emac_enable_zmii_port(struct ocp_device *ocpdev, int input) +{ + u32 mask; + struct ibm_ocp_zmii *zmii = ZMII_PRIV(ocpdev); + + mask = in_be32(&zmii->base->fer); + mask &= zmii_enable[input][MDI]; /* turn all non enabled MDI's off */ + mask |= zmii_enable[input][zmii->mode] | mdi_enable[input]; + out_be32(&zmii->base->fer, mask); +} + +static void +emac_zmii_port_speed(struct ocp_device *ocpdev, int input, int speed) +{ + struct ibm_ocp_zmii *zmii = ZMII_PRIV(ocpdev); + + if (speed == 100) + zmii_speed |= zmii_speed100[input]; + else + zmii_speed &= ~zmii_speed100[input]; + + out_be32(&zmii->base->ssr, zmii_speed); +} + +static void +emac_fini_zmii(struct ocp_device *ocpdev) +{ + struct ibm_ocp_zmii *zmii = ZMII_PRIV(ocpdev); + BUG_ON(!zmii || zmii->users == 0); + + if (!--zmii->users){ + ocp_set_drvdata(ocpdev, NULL); + iounmap((void*)zmii->base); + kfree(zmii); + } +} + +int +emac_phy_read(struct net_device *dev, int mii_id, int reg) +{ + register int i; + uint32_t stacr; + struct ocp_enet_private *fep = dev->priv; + volatile emac_t *emacp = fep->emacp; + + MDIO_DEBUG(("%s: phy_read, id: 0x%x, reg: 0x%x\n", dev->name, mii_id, reg)); + + /* Enable proper ZMII port */ + if (fep->zmii_dev) + emac_enable_zmii_port(fep->zmii_dev, fep->zmii_input); + /* Use the EMAC that has the MDIO port */ + if (fep->mdio_dev) { + dev = fep->mdio_dev; + fep = dev->priv; + } + + /* Wait for data transfer complete bit */ + for (i = 0; i < OCP_RESET_DELAY; ++i) { + if (emacp->em0stacr & EMAC_STACR_OC) + break; + udelay(MDIO_DELAY); /* changed to 2 with new scheme -armin */ + } + if ((emacp->em0stacr & EMAC_STACR_OC) == 0) { + printk(KERN_WARNING "%s: PHY read timeout #1!\n", dev->name); + return -1; + } + + /* Clear the speed bits and make a read request to the PHY */ + stacr = ((EMAC_STACR_READ | (reg & 0x1f)) & ~EMAC_STACR_CLK_100MHZ); + stacr |= ((mii_id & 0x1F) << 5); + + out_be32(&emacp->em0stacr, stacr); + stacr = in_be32(&emacp->em0stacr); + /* Wait for data transfer complete bit */ + for (i = 0; i < OCP_RESET_DELAY; ++i) { + if ((stacr = in_be32(&emacp->em0stacr)) & EMAC_STACR_OC) + break; + udelay(MDIO_DELAY); + } + if ((stacr & EMAC_STACR_OC) == 0) { + printk(KERN_WARNING "%s: PHY read timeout #2!\n", dev->name); + return -1; + } + + /* Check for a read error */ + if (stacr & EMAC_STACR_PHYE) { + MDIO_DEBUG(("OCP MDIO PHY error !\n")); + return -1; + } + + MDIO_DEBUG((" -> 0x%x\n", stacr >> 16)); + + return (stacr >> 16); +} + + +void +emac_phy_write(struct net_device *dev, int mii_id, int reg, int data) +{ + register int i = 0; + uint32_t stacr; + struct ocp_enet_private *fep = dev->priv; + volatile emac_t *emacp = fep->emacp; + + MDIO_DEBUG(("%s phy_write, id: 0x%x, reg: 0x%x, data: 0x%x\n", + dev->name, mii_id, reg, data)); + + /* Enable proper ZMII port */ + if (fep->zmii_dev) + emac_enable_zmii_port(fep->zmii_dev, fep->zmii_input); + /* Use the EMAC that has the MDIO port */ + if (fep->mdio_dev) { + dev = fep->mdio_dev; + fep = dev->priv; + } + + /* Wait for data transfer complete bit */ + for (i = 0; i < OCP_RESET_DELAY; ++i) { + if (emacp->em0stacr & EMAC_STACR_OC) + break; + udelay(MDIO_DELAY); /* changed to 2 with new scheme -armin */ + } + if ((emacp->em0stacr & EMAC_STACR_OC) == 0) { + printk(KERN_WARNING "%s: PHY write timeout #2!\n", dev->name); + return; + } + + /* Clear the speed bits and make a read request to the PHY */ + + stacr = ((EMAC_STACR_WRITE | (reg & 0x1f)) & ~EMAC_STACR_CLK_100MHZ); + stacr |= ((mii_id & 0x1f) << 5) | ((data & 0xffff) << 16); + + out_be32(&emacp->em0stacr, stacr); + + /* Wait for data transfer complete bit */ + for (i = 0; i < OCP_RESET_DELAY; ++i) { + if ((stacr = emacp->em0stacr) & EMAC_STACR_OC) + break; + udelay(MDIO_DELAY); + } + if ((emacp->em0stacr & EMAC_STACR_OC) == 0) + printk(KERN_WARNING "%s: PHY write timeout #2!\n", dev->name); + + /* Check for a write error */ + if ((stacr & EMAC_STACR_PHYE) != 0) { + MDIO_DEBUG(("OCP MDIO PHY error !\n")); + } +} + +static void +emac_wakeup_irq(int irq, void *param, struct pt_regs *regs) +{ + struct net_device *dev = param; + + /* On Linux the 405 ethernet will always be active if configured + * in. This interrupt should never occur. + */ + printk(KERN_INFO "%s: WakeUp interrupt !\n", dev->name); +} + +static void +emac_txeob_dev(void *param, u32 chanmask) +{ + struct net_device *dev = param; + struct ocp_enet_private *fep = dev->priv; + unsigned long flags; + + spin_lock_irqsave(&fep->lock, flags); + + PKT_DEBUG(("emac_txeob_dev() entry, tx_cnt: %d\n", fep->tx_cnt)); + + while (fep->tx_cnt && + !(fep->tx_desc[fep->ack_slot].ctrl & MAL_TX_CTRL_READY)) { + + /* Tell the system the transmit completed. */ + dev_kfree_skb_irq(fep->tx_skb[fep->ack_slot]); + + if (fep->tx_desc[fep->ack_slot].ctrl & + (EMAC_TX_ST_EC | EMAC_TX_ST_MC | EMAC_TX_ST_SC)) + fep->stats.collisions++; + + fep->tx_skb[fep->ack_slot] = (struct sk_buff *) NULL; + if (++fep->ack_slot == NUM_TX_BUFF) + fep->ack_slot = 0; + + fep->tx_cnt--; + } + if (fep->tx_cnt < NUM_TX_BUFF) + netif_wake_queue(dev); + + PKT_DEBUG(("emac_txeob_dev() exit, tx_cnt: %d\n", fep->tx_cnt)); + + spin_unlock_irqrestore(&fep->lock, flags); +} + +/* + Fill/Re-fill the rx chain with valid ctrl/ptrs. + This function will fill from rx_slot up to the parm end. + So to completely fill the chain pre-set rx_slot to 0 and + pass in an end of 0. + */ +static void +emac_rx_fill(struct net_device *dev, int end) +{ + int i; + struct ocp_enet_private *fep = dev->priv; + unsigned char *ptr; + + i = fep->rx_slot; + do { + if (fep->rx_skb[i] != NULL) { + /*We will trust the skb is still in a good state */ + ptr = (char *) virt_to_phys(fep->rx_skb[i]->data); + } else { + + /* We don't want the 16 bytes skb_reserve done by dev_alloc_skb, + * it breaks our cache line alignement. However, we still allocate + * +16 so that we end up allocating the exact same size as + * dev_alloc_skb() would do. + * Also, because of the skb_res, the max DMA size we give to EMAC + * is slighly wrong, causing it to potentially DMA 2 more bytes + * from a broken/oversized packet. These 16 bytes will take care + * that we don't walk on somebody else toes with that. + */ + fep->rx_skb[i] = + alloc_skb(DESC_RX_BUF_SIZE + 16, GFP_ATOMIC); + + if (fep->rx_skb[i] == NULL) { + /* Keep rx_slot here, the next time clean/fill is called + * we will try again before the MAL wraps back here + * If the MAL tries to use this descriptor with + * the EMPTY bit off it will cause the + * rxde interrupt. That is where we will + * try again to allocate an sk_buff. + */ + break; + + } + + if (skb_res) + skb_reserve(fep->rx_skb[i], skb_res); + + /* We must NOT consistent_sync the cache line right after the + * buffer, so we must crop our sync size to account for the + * reserved space + */ + consistent_sync((void *) fep->rx_skb[i]-> + data, (DESC_RX_BUF_SIZE-skb_res), + PCI_DMA_FROMDEVICE); + ptr = (char *) virt_to_phys(fep->rx_skb[i]->data); + } + fep->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR | /*could be smarter about this to avoid ints at high loads */ + (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0); + + fep->rx_desc[i].data_ptr = ptr; + /* + * 440GP uses the previously reserved bits in the + * data_len to encode the upper 4-bits of the buffer + * physical address (ERPN). Initialize these. + */ + fep->rx_desc[i].data_len = 0; + } while ((i = (i + 1) % NUM_RX_BUFF) != end); + + fep->rx_slot = i; +} + +static void +emac_rx_clean(struct net_device *dev, int call_rx_fill) +{ + int i; + int error, frame_length; + struct ocp_enet_private *fep = dev->priv; + unsigned short ctrl; + int slots_walked = 0; + + i = fep->rx_slot; + + PKT_DEBUG(("emac_rx_clean() entry, call_rx_fill: %d, rx_slot: %d\n", call_rx_fill, fep->rx_slot)); + + do { + if (fep->rx_skb[i] == NULL) + goto skip; /*we have already handled the packet but haved failed to alloc */ + /* + since rx_desc is in uncached mem we don't keep reading it directly + we pull out a local copy of ctrl and do the checks on the copy. + */ + ctrl = fep->rx_desc[i].ctrl; + if (ctrl & MAL_RX_CTRL_EMPTY) + break; /*we don't have any more ready packets */ + + if (ctrl & EMAC_BAD_RX_PACKET) { + + fep->stats.rx_errors++; + fep->stats.rx_dropped++; + + if (ctrl & EMAC_RX_ST_OE) + fep->stats.rx_fifo_errors++; + if (ctrl & EMAC_RX_ST_AE) + fep->stats.rx_frame_errors++; + if (ctrl & EMAC_RX_ST_BFCS) + fep->stats.rx_crc_errors++; + if (ctrl & (EMAC_RX_ST_RP | EMAC_RX_ST_PTL | + EMAC_RX_ST_ORE | EMAC_RX_ST_IRE)) + fep->stats.rx_length_errors++; + } else { + + /* Send the skb up the chain. */ + frame_length = fep->rx_desc[i].data_len - 4; + + skb_put(fep->rx_skb[i], frame_length); + fep->rx_skb[i]->dev = dev; + fep->rx_skb[i]->protocol = + eth_type_trans(fep->rx_skb[i], dev); + + error = netif_rx(fep->rx_skb[i]); + if ((error == NET_RX_DROP) || (error == NET_RX_BAD)) { + fep->stats.rx_dropped++; + } else { + fep->stats.rx_packets++; + fep->stats.rx_bytes += frame_length; + } + fep->rx_skb[i] = NULL; + } + skip: + slots_walked = 1; + + } while ((i = (i + 1) % NUM_RX_BUFF) != fep->rx_slot); + + PKT_DEBUG(("emac_rx_clean() exit, rx_slot: %d\n", fep->rx_slot)); + + if (slots_walked && call_rx_fill) + emac_rx_fill(dev, i); +} + +static void +emac_rxeob_dev(void *param, u32 chanmask) +{ + struct net_device *dev = param; + struct ocp_enet_private *fep = dev->priv; + unsigned long flags; + + spin_lock_irqsave(&fep->lock, flags); + emac_rx_clean(dev, 1); + spin_unlock_irqrestore(&fep->lock, flags); +} + +/* + * This interrupt should never occurr, we don't program + * the MAL for contiunous mode. + */ +static void +emac_txde_dev(void *param, u32 chanmask) +{ + struct net_device *dev = param; + struct ocp_enet_private *fep = dev->priv; + + printk(KERN_WARNING "%s: transmit descriptor error\n", dev->name); + + emac_mac_dump(dev); + emac_mal_dump(dev); + + /* Reenable the transmit channel */ + mal_enable_tx_channels(fep->mal, fep->commac.tx_chan_mask); +} + +/* + * This interrupt should be very rare at best. This occurs when + * the hardware has a problem with the receive descriptors. The manual + * states that it occurs when the hardware cannot the receive descriptor + * empty bit is not set. The recovery mechanism will be to + * traverse through the descriptors, handle any that are marked to be + * handled and reinitialize each along the way. At that point the driver + * will be restarted. + */ +static void +emac_rxde_dev(void *param, u32 chanmask) +{ + struct net_device *dev = param; + struct ocp_enet_private *fep = dev->priv; + unsigned long flags; + + printk(KERN_WARNING "%s: receive descriptor error\n", fep->ndev->name); + + emac_mac_dump(dev); + emac_mal_dump(dev); + emac_desc_dump(dev); + + /* Disable RX channel */ + spin_lock_irqsave(&fep->lock, flags); + mal_disable_rx_channels(fep->mal, fep->commac.rx_chan_mask); + + /* For now, charge the error against all emacs */ + fep->stats.rx_errors++; + + /* so do we have any good packets still? */ + emac_rx_clean(dev,0); + + /* When the interface is restarted it resets processing to the + * first descriptor in the table. + */ + + fep->rx_slot = 0; + emac_rx_fill(dev, 0); + + set_mal_dcrn(fep->mal, DCRN_MALRXEOBISR, fep->commac.rx_chan_mask); + set_mal_dcrn(fep->mal, DCRN_MALRXDEIR, fep->commac.rx_chan_mask); + + /* Reenable the receive channels */ + mal_enable_rx_channels(fep->mal, fep->commac.rx_chan_mask); + spin_unlock_irqrestore(&fep->lock, flags); +} + +static void +emac_mac_irq(int irq, void *dev_instance, struct pt_regs *regs) +{ + struct net_device *dev = dev_instance; + struct ocp_enet_private *fep = dev->priv; + volatile emac_t *emacp = fep->emacp; + unsigned long tmp_em0isr; + + /* EMAC interrupt */ + tmp_em0isr = in_be32(&emacp->em0isr); + if (tmp_em0isr & (EMAC_ISR_TE0 | EMAC_ISR_TE1)) { + /* This error is a hard transmit error - could retransmit */ + fep->stats.tx_errors++; + + /* Reenable the transmit channel */ + mal_enable_tx_channels(fep->mal, fep->commac.tx_chan_mask); + + } else { + fep->stats.rx_errors++; + } + + if (tmp_em0isr & EMAC_ISR_RP) + fep->stats.rx_length_errors++; + if (tmp_em0isr & EMAC_ISR_ALE) + fep->stats.rx_frame_errors++; + if (tmp_em0isr & EMAC_ISR_BFCS) + fep->stats.rx_crc_errors++; + if (tmp_em0isr & EMAC_ISR_PTLE) + fep->stats.rx_length_errors++; + if (tmp_em0isr & EMAC_ISR_ORE) + fep->stats.rx_length_errors++; + if (tmp_em0isr & EMAC_ISR_TE0) + fep->stats.tx_aborted_errors++; + + emac_err_dump(dev, tmp_em0isr); + + out_be32(&emacp->em0isr, tmp_em0isr); +} + +static int +emac_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + unsigned short ctrl; + unsigned long flags; + struct ocp_enet_private *fep = dev->priv; + volatile emac_t *emacp = fep->emacp; + + spin_lock_irqsave(&fep->lock, flags); + + PKT_DEBUG(("emac_start_xmit() entry, queue stopped: %d, fep->tx_cnt: %d\n", + netif_queue_stopped(dev), fep->tx_cnt)); + + /* That shouldn't happen... */ + if (netif_queue_stopped(dev) || (fep->tx_cnt == NUM_TX_BUFF)) { + printk("%s: start_xmit called on full queue !\n", dev->name); + BUG(); + } + + if (++fep->tx_cnt == NUM_TX_BUFF) { + PKT_DEBUG(("emac_start_xmit() stopping queue\n")); + netif_stop_queue(dev); + } + + /* Store the skb buffer for later ack by the transmit end of buffer + * interrupt. + */ + fep->tx_skb[fep->tx_slot] = skb; + consistent_sync((void *) skb->data, skb->len, PCI_DMA_TODEVICE); + + ctrl = EMAC_TX_CTRL_DFLT; + if ((NUM_TX_BUFF - 1) == fep->tx_slot) + ctrl |= MAL_TX_CTRL_WRAP; + fep->tx_desc[fep->tx_slot].data_ptr = (char *) virt_to_phys(skb->data); + fep->tx_desc[fep->tx_slot].data_len = (short) skb->len; + fep->tx_desc[fep->tx_slot].ctrl = ctrl; + + /* Send the packet out. */ + out_be32(&emacp->em0tmr0, EMAC_TMR0_XMIT); + + if (++fep->tx_slot == NUM_TX_BUFF) + fep->tx_slot = 0; + + fep->stats.tx_packets++; + fep->stats.tx_bytes += skb->len; + + PKT_DEBUG(("emac_start_xmit() exitn")); + + spin_unlock_irqrestore(&fep->lock, flags); + + return 0; +} + +static int +emac_adjust_to_link(struct ocp_enet_private *fep) +{ + volatile emac_t *emacp = fep->emacp; + unsigned long mode_reg; + int full_duplex, speed; + + full_duplex = 0; + speed = SPEED_10; + + /* set mode register 1 defaults */ + mode_reg = EMAC_M1_DEFAULT; + + /* Read link mode on PHY */ + if (fep->phy_mii.def->ops->read_link(&fep->phy_mii) == 0) { + /* If an error occurred, we don't deal with it yet */ + full_duplex = (fep->phy_mii.duplex == DUPLEX_FULL); + speed = fep->phy_mii.speed; + } + + /* set speed (default is 10Mb) */ + if (speed == SPEED_100) { + mode_reg |= EMAC_M1_MF_100MBPS; + if (fep->zmii_dev) + emac_zmii_port_speed(fep->zmii_dev, fep->zmii_input, 100); + } else { + mode_reg &= ~EMAC_M1_MF_100MBPS; + if (fep->zmii_dev) + emac_zmii_port_speed(fep->zmii_dev, fep->zmii_input, 10); + } + + if (full_duplex) + mode_reg |= EMAC_M1_FDE | EMAC_M1_EIFC | EMAC_M1_IST; + else + mode_reg &= ~(EMAC_M1_FDE | EMAC_M1_EIFC | EMAC_M1_ILE); + + LINK_DEBUG(("%s: adjust to link, speed: %d, duplex: %d, opened: %d\n", + fep->ndev->name, speed, full_duplex, fep->opened)); + + printk(KERN_INFO "%s: Speed: %s, %s duplex.\n", + fep->ndev->name, + speed == SPEED_100 ? "100" : "10", + full_duplex ? "Full" : "Half"); + if (fep->opened) + out_be32(&emacp->em0mr1, mode_reg); + + return 0; +} + +static void +__emac_set_multicast_list(struct net_device *dev) +{ + struct ocp_enet_private *fep = dev->priv; + volatile emac_t *emacp = fep->emacp; + u32 rmr = in_be32(&emacp->em0rmr); + + /* First clear all special bits, they can be set later */ + rmr &= ~(EMAC_RMR_PME | EMAC_RMR_PMME | EMAC_RMR_MAE); + + if (dev->flags & IFF_PROMISC) { + rmr |= EMAC_RMR_PME; + + } else if (dev->flags & IFF_ALLMULTI || 32 < dev->mc_count) { + /* Must be setting up to use multicast. Now check for promiscuous + * multicast + */ + rmr |= EMAC_RMR_PMME; + } else if (dev->flags & IFF_MULTICAST && 0 < dev->mc_count) { + + unsigned short em0gaht[4] = { 0, 0, 0, 0 }; + struct dev_mc_list *dmi; + + /* Need to hash on the multicast address. */ + for (dmi = dev->mc_list; dmi; dmi = dmi->next) { + unsigned long mc_crc; + unsigned int bit_number; + + mc_crc = ether_crc(6, (char *) dmi->dmi_addr); + bit_number = 63 - (mc_crc >> 26); /* MSB: 0 LSB: 63 */ + em0gaht[bit_number >> 4] |= + 0x8000 >> (bit_number & 0x0f); + } + emacp->em0gaht1 = em0gaht[0]; + emacp->em0gaht2 = em0gaht[1]; + emacp->em0gaht3 = em0gaht[2]; + emacp->em0gaht4 = em0gaht[3]; + + /* Turn on multicast addressing */ + rmr |= EMAC_RMR_MAE; + } + + out_be32(&emacp->em0rmr, rmr); +} + +static void +emac_init_rings(struct net_device *dev) +{ + struct ocp_enet_private *ep = dev->priv; + int loop; + + ep->tx_desc = (struct mal_descriptor *) ((char *) ep->mal->tx_virt_addr + + (ep->mal_tx_chan * MAL_DT_ALIGN)); + ep->rx_desc = (struct mal_descriptor *) ((char *) ep->mal->rx_virt_addr + + (ep->mal_rx_chan * MAL_DT_ALIGN)); + + /* Fill in the transmit descriptor ring. */ + for (loop = 0; loop < NUM_TX_BUFF; loop++) { + if (ep->tx_skb[loop]) + dev_kfree_skb_irq(ep->tx_skb[loop]); + ep->tx_skb[loop] = NULL; + ep->tx_desc[loop].ctrl = 0; + ep->tx_desc[loop].data_len = 0; + ep->tx_desc[loop].data_ptr = NULL; + } + ep->tx_desc[loop - 1].ctrl |= MAL_TX_CTRL_WRAP; + + /* Format the receive descriptor ring. */ + ep->rx_slot = 0; + emac_rx_fill(dev, 0); + if (ep->rx_slot != 0) { + printk(KERN_ERR + "%s: Not enough mem for RxChain durning Open?\n", + dev->name); + /*We couldn't fill the ring at startup? + *We could clean up and fail to open but right now we will try to + *carry on. It may be a sign of a bad NUM_RX_BUFF value + */ + } + + ep->tx_cnt = 0; + ep->tx_slot = 0; + ep->ack_slot = 0; +} + +static void +emac_reset_configure(struct ocp_enet_private *fep) +{ + volatile emac_t *emacp = fep->emacp; + int i; + + mal_disable_tx_channels(fep->mal, fep->commac.tx_chan_mask); + mal_disable_rx_channels(fep->mal, fep->commac.rx_chan_mask); + + /* Reset the EMAC */ + out_be32(&emacp->em0mr0, EMAC_M0_SRST); + udelay(20); + for (i=0; i<100; i++) { + if ((in_be32(&emacp->em0mr0) & EMAC_M0_SRST) == 0) + break; + udelay(10); + } + + if (i >= 100) { + printk(KERN_ERR "%s: Cannot reset EMAC\n", fep->ndev->name); + return; + } + + /* Switch IRQs off for now */ + out_be32(&emacp->em0iser, 0); + + /* Configure MAL rx channel */ + mal_set_rcbs(fep->mal, fep->mal_rx_chan, DESC_BUF_SIZE_REG); + + /* set the high address */ + out_be32(&emacp->em0iahr, (fep->ndev->dev_addr[0] << 8) | fep->ndev->dev_addr[1]); + + /* set the low address */ + out_be32(&emacp->em0ialr, + (fep->ndev->dev_addr[2] << 24) | (fep->ndev->dev_addr[3] << 16) + | (fep->ndev->dev_addr[4] << 8) | fep->ndev->dev_addr[5]); + + /* Adjust to link */ + if (netif_carrier_ok(fep->ndev)) + emac_adjust_to_link(fep); + + /* enable broadcast/individual address and RX FIFO defaults */ + out_be32(&emacp->em0rmr, EMAC_RMR_DEFAULT); + + /* set transmit request threshold register */ + out_be32(&emacp->em0trtr, EMAC_TRTR_DEFAULT); + + /* Reconfigure multicast */ + __emac_set_multicast_list(fep->ndev); + + /* Set receiver/transmitter defaults */ + out_be32(&emacp->em0rwmr, EMAC_RWMR_DEFAULT); + out_be32(&emacp->em0tmr0, EMAC_TMR0_DEFAULT); + out_be32(&emacp->em0tmr1, EMAC_TMR1_DEFAULT); + + /* set frame gap */ + out_be32(&emacp->em0ipgvr, CONFIG_IBM_OCP_ENET_GAP); + + /* Init ring buffers */ + emac_init_rings(fep->ndev); +} + +static void +emac_kick(struct ocp_enet_private *fep) +{ + volatile emac_t *emacp = fep->emacp; + unsigned long emac_ier; + + emac_ier = EMAC_ISR_PP | EMAC_ISR_BP | EMAC_ISR_RP | + EMAC_ISR_SE | EMAC_ISR_PTLE | EMAC_ISR_ALE | + EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; + + out_be32(&emacp->em0iser, emac_ier); + + /* enable all MAL transmit and receive channels */ + mal_enable_tx_channels(fep->mal, fep->commac.tx_chan_mask); + mal_enable_rx_channels(fep->mal, fep->commac.rx_chan_mask); + + /* set transmit and receive enable */ + out_be32(&emacp->em0mr0, EMAC_M0_TXE | EMAC_M0_RXE); +} + +static void +emac_start_link(struct ocp_enet_private *fep, struct ethtool_cmd *ep) +{ + u32 advertise; + int autoneg; + int forced_speed; + int forced_duplex; + + /* Default advertise */ + advertise = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | + ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; + autoneg = fep->want_autoneg; + forced_speed = fep->phy_mii.speed; + forced_duplex = fep->phy_mii.duplex; + + /* Setup link parameters */ + if (ep) { + if (ep->autoneg == AUTONEG_ENABLE) { + advertise = ep->advertising; + autoneg = 1; + } else { + autoneg = 0; + forced_speed = ep->speed; + forced_duplex = ep->duplex; + } + } + + /* Configure PHY & start aneg */ + fep->want_autoneg = autoneg; + if (autoneg) { + LINK_DEBUG(("%s: start link aneg, advertise: 0x%x\n", + fep->ndev->name, advertise)); + fep->phy_mii.def->ops->setup_aneg(&fep->phy_mii, advertise); + } else { + LINK_DEBUG(("%s: start link forced, speed: %d, duplex: %d\n", + fep->ndev->name, forced_speed, forced_duplex)); + fep->phy_mii.def->ops->setup_forced(&fep->phy_mii, forced_speed, + forced_duplex); + } + fep->timer_ticks = 0; + mod_timer(&fep->link_timer, jiffies + HZ); +} + +static void +emac_link_timer(unsigned long data) +{ + struct ocp_enet_private *fep = (struct ocp_enet_private *)data; + int link; + + if (fep->going_away) + return; + + spin_lock_irq(&fep->lock); + + link = fep->phy_mii.def->ops->poll_link(&fep->phy_mii); + LINK_DEBUG(("%s: poll_link: %d\n", fep->ndev->name, link)); + + if (link == netif_carrier_ok(fep->ndev)) { + if (!link && fep->want_autoneg && (++fep->timer_ticks) > 10) + emac_start_link(fep, NULL); + goto out; + } + printk(KERN_INFO "%s: Link is %s\n", fep->ndev->name, link ? "Up" : "Down"); + if (link) { + netif_carrier_on(fep->ndev); + /* Chip needs a full reset on config change. That sucks, so I + * should ultimately move that to some tasklet to limit + * latency peaks caused by this code + */ + emac_reset_configure(fep); + if (fep->opened) + emac_kick(fep); + } else { + fep->timer_ticks = 0; + netif_carrier_off(fep->ndev); + } +out: + mod_timer(&fep->link_timer, jiffies + HZ); + spin_unlock_irq(&fep->lock); +} + +static void +emac_set_multicast_list(struct net_device *dev) +{ + struct ocp_enet_private *fep = dev->priv; + + spin_lock_irq(&fep->lock); + __emac_set_multicast_list(dev); + spin_unlock_irq(&fep->lock); +} + +static int +emac_ethtool(struct net_device *dev, void* ep_user) +{ + struct ocp_enet_private *fep = dev->priv; + struct ethtool_cmd ecmd; + unsigned long features = fep->phy_mii.def->features; + + if (copy_from_user(&ecmd, ep_user, sizeof(ecmd))) + return -EFAULT; + + switch(ecmd.cmd) { + case ETHTOOL_GDRVINFO: { + struct ethtool_drvinfo info; + memset(&info, 0, sizeof(info)); + info.cmd = ETHTOOL_GDRVINFO; + strncpy(info.driver, DRV_NAME, ETHTOOL_BUSINFO_LEN); + strncpy(info.version, DRV_VERSION, ETHTOOL_BUSINFO_LEN); + info.fw_version[0] = '\0'; + sprintf(info.bus_info, "OCP EMAC %d", fep->ocpdev->def->index); + info.regdump_len = 0; + if (copy_to_user(ep_user, &info, sizeof(info))) + return -EFAULT; + return 0; + } + + case ETHTOOL_GSET: + ecmd.supported = features; + ecmd.port = PORT_MII; + ecmd.transceiver = XCVR_EXTERNAL; + ecmd.phy_address = fep->mii_phy_addr; + spin_lock_irq(&fep->lock); + ecmd.autoneg = fep->want_autoneg; + ecmd.speed = fep->phy_mii.speed; + ecmd.duplex = fep->phy_mii.duplex; + spin_unlock_irq(&fep->lock); + if (copy_to_user(ep_user, &ecmd, sizeof(ecmd))) + return -EFAULT; + return 0; + + case ETHTOOL_SSET: + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + + if (ecmd.autoneg != AUTONEG_ENABLE && + ecmd.autoneg != AUTONEG_DISABLE) + return -EINVAL; + if (ecmd.autoneg == AUTONEG_ENABLE && + ecmd.advertising == 0) + return -EINVAL; + if (ecmd.duplex != DUPLEX_HALF && ecmd.duplex != DUPLEX_FULL) + return -EINVAL; + if (ecmd.autoneg == AUTONEG_DISABLE) + switch(ecmd.speed) { + case SPEED_10: + if (ecmd.duplex == DUPLEX_HALF && + (features & SUPPORTED_10baseT_Half) == 0) + return -EINVAL; + if (ecmd.duplex == DUPLEX_FULL && + (features & SUPPORTED_10baseT_Full) == 0) + return -EINVAL; + break; + case SPEED_100: + if (ecmd.duplex == DUPLEX_HALF && + (features & SUPPORTED_100baseT_Half) == 0) + return -EINVAL; + if (ecmd.duplex == DUPLEX_FULL && + (features & SUPPORTED_100baseT_Full) == 0) + return -EINVAL; + break; + default: + return -EINVAL; + } + else if ((features & SUPPORTED_Autoneg) == 0) + return -EINVAL; + spin_lock_irq(&fep->lock); + emac_start_link(fep, &ecmd); + spin_unlock_irq(&fep->lock); + return 0; + + case ETHTOOL_NWAY_RST: + if (!fep->want_autoneg) + return -EINVAL; + spin_lock_irq(&fep->lock); + emac_start_link(fep, NULL); + spin_unlock_irq(&fep->lock); + return 0; + + case ETHTOOL_GLINK: { + struct ethtool_value edata; + memset(&edata, 0, sizeof(edata)); + edata.cmd = ETHTOOL_GLINK; + edata.data = netif_carrier_ok(dev); + if (copy_to_user(ep_user, &edata, sizeof(edata))) + return -EFAULT; + return 0; + } + } + + return -EOPNOTSUPP; +} + +static int +emac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + struct ocp_enet_private *fep = dev->priv; + uint *data = (uint *) & rq->ifr_data; + + switch (cmd) { + case SIOCETHTOOL: + return emac_ethtool(dev, rq->ifr_data); + case SIOCDEVPRIVATE: + case SIOCGMIIPHY: + data[0] = fep->mii_phy_addr; + /*FALLTHRU*/ + case SIOCDEVPRIVATE + 1: + case SIOCGMIIREG: + data[3] = emac_phy_read(dev, fep->mii_phy_addr, data[1]); + return 0; + case SIOCDEVPRIVATE + 2: + case SIOCSMIIREG: + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + + emac_phy_write(dev, fep->mii_phy_addr, data[1], data[2]); + return 0; + default: + return -EOPNOTSUPP; + } +} + +static int +emac_open(struct net_device *dev) +{ + struct ocp_enet_private *fep = dev->priv; + int rc; + + spin_lock_irq(&fep->lock); + + fep->opened = 1; + + /* Reset & configure the chip */ + emac_reset_configure(fep); + + spin_unlock_irq(&fep->lock); + + /* Request our interrupt lines */ + rc = request_irq(dev->irq, emac_mac_irq, 0, "OCP EMAC MAC", dev); + if (rc != 0) + goto bail; + rc = request_irq(fep->wol_irq, emac_wakeup_irq, 0, "OCP EMAC Wakeup", dev); + if (rc != 0) { + free_irq(dev->irq, dev); + goto bail; + } + /* Kick the chip rx & tx channels into life */ + spin_lock_irq(&fep->lock); + emac_kick(fep); + spin_unlock_irq(&fep->lock); + + netif_start_queue(dev); +bail: + return rc; +} + +static int +emac_close(struct net_device *dev) +{ + struct ocp_enet_private *fep = dev->priv; + volatile emac_t *emacp = fep->emacp; + + /* XXX Stop IRQ emitting here */ + spin_lock_irq(&fep->lock); + fep->opened = 0; + mal_disable_tx_channels(fep->mal, fep->commac.tx_chan_mask); + mal_disable_rx_channels(fep->mal, fep->commac.rx_chan_mask); + netif_stop_queue(dev); + + out_be32(&emacp->em0mr0, EMAC_M0_SRST); + udelay(10); + + if (emacp->em0mr0 & EMAC_M0_SRST) { + /*not sure what to do here hopefully it clears before another open */ + printk(KERN_ERR "%s: Phy SoftReset didn't clear, no link?\n", + dev->name); + } + + /* Free the irq's */ + free_irq(dev->irq, dev); + free_irq(fep->wol_irq, dev); + + spin_unlock_irq(&fep->lock); + + return 0; +} + +static void +emac_remove(struct ocp_device *ocpdev) +{ + struct net_device *dev = ocp_get_drvdata(ocpdev); + struct ocp_enet_private *ep = dev->priv; + + /* FIXME: locking, races, ... */ + ep->going_away = 1; + ocp_set_drvdata(ocpdev, NULL); + if (ep->zmii_dev) + emac_fini_zmii(ep->zmii_dev); + + unregister_netdev(dev); + del_timer_sync(&ep->link_timer); + mal_unregister_commac(ep->mal, &ep->commac); + iounmap((void *)ep->emacp); + kfree(dev); +} + +struct mal_commac_ops emac_commac_ops = { + .txeob = &emac_txeob_dev, + .txde = &emac_txde_dev, + .rxeob = &emac_rxeob_dev, + .rxde = &emac_rxde_dev, +}; + +static int +emac_probe(struct ocp_device *ocpdev) +{ + int rc = 0, i; + bd_t *bd; + struct net_device *ndev; + struct ocp_enet_private *ep; + struct ocp_device *maldev; + struct ibm_ocp_mal *mal; + struct ocp_func_emac_data *emacdata; + struct ocp_device *mdiodev; + struct net_device *mdio_ndev = NULL; + int commac_reg = 0; + u32 phy_map; + + emacdata = (struct ocp_func_emac_data *)ocpdev->def->additions; + if (emacdata == NULL) { + printk(KERN_ERR "emac%d: Missing additional datas !\n", ocpdev->def->index); + return -ENODEV; + } + + /* Wait for MAL to show up */ + maldev = ocp_find_device(OCP_ANY_ID, OCP_FUNC_MAL, emacdata->mal_idx); + if (maldev == NULL) + return -EAGAIN; + /* Check if MAL driver attached yet */ + mal = (struct ibm_ocp_mal *)ocp_get_drvdata(maldev); + if (mal == NULL) + return -EAGAIN; + + /* If we depend on another EMAC for MDIO, wait for it to show up */ + if (emacdata->mdio_idx >= 0 && emacdata->mdio_idx != ocpdev->def->index) { + mdiodev = ocp_find_device(OCP_ANY_ID, OCP_FUNC_EMAC, emacdata->mdio_idx); + if (mdiodev == NULL) + return -EAGAIN; + mdio_ndev = (struct net_device *)ocp_get_drvdata(mdiodev); + if (mdio_ndev == NULL) + return -EAGAIN; + } + + /* Allocate our net_device structure */ + ndev = alloc_etherdev(sizeof (struct ocp_enet_private)); + if (ndev == NULL) { + printk(KERN_ERR + "emac%d: Could not allocate ethernet device.\n", ocpdev->def->index); + return -ENOMEM; + } + ep = ndev->priv; + memset(ep, 0, sizeof(*ep)); + ep->ndev = ndev; + ep->ocpdev = ocpdev; + ndev->irq = ocpdev->def->irq; + ep->wol_irq = emacdata->wol_irq; + ep->mdio_dev = mdio_ndev; + ocp_set_drvdata(ocpdev, ndev); + spin_lock_init(&ep->lock); + + /* Fill out MAL informations and register commac */ + ep->mal = mal; + ep->mal_tx_chan = emacdata->mal_tx1_chan; + ep->mal_rx_chan = emacdata->mal_rx_chan; + ep->commac.ops = &emac_commac_ops; + ep->commac.dev = ndev; + ep->commac.tx_chan_mask = MAL_CHAN_MASK(ep->mal_tx_chan); + ep->commac.rx_chan_mask = MAL_CHAN_MASK(ep->mal_rx_chan); + rc = mal_register_commac(ep->mal, &ep->commac); + if (rc != 0) + goto bail; + commac_reg = 1; + + /* Map our MMIOs */ + ep->emacp = (volatile emac_t *)ioremap(ocpdev->def->paddr, sizeof (emac_t)); + + /* Check if we need to attach to a ZMII */ + if (emacdata->zmii_idx >= 0) { + ep->zmii_input = emacdata->zmii_mux; + ep->zmii_dev = ocp_find_device(OCP_ANY_ID, OCP_FUNC_ZMII, emacdata->zmii_idx); + if (ep->zmii_dev == NULL) + printk(KERN_WARNING "emac%d: ZMII %d requested but not found !\n", + ocpdev->def->index, emacdata->zmii_idx); + else if ((rc = emac_init_zmii(ep->zmii_dev, ZMII_AUTO)) != 0) + goto bail; + } + + /* Reset the EMAC */ + out_be32(&ep->emacp->em0mr0, EMAC_M0_SRST); + udelay(20); + for (i=0; i<100; i++) { + if ((in_be32(&ep->emacp->em0mr0) & EMAC_M0_SRST) == 0) + break; + udelay(10); + } + + if (i >= 100) { + printk(KERN_ERR "emac%d: Cannot reset EMAC\n", ocpdev->def->index); + rc = -ENXIO; + goto bail; + } + + /* Init link monitoring timer */ + init_timer(&ep->link_timer); + ep->link_timer.function = emac_link_timer; + ep->link_timer.data = (unsigned long) ep; + ep->timer_ticks = 0; + + /* Fill up the mii_phy structure */ + ep->phy_mii.dev = ndev; + ep->phy_mii.mdio_read = emac_phy_read; + ep->phy_mii.mdio_write = emac_phy_write; + + /* Find PHY */ + phy_map = emac_phy_map[ocpdev->def->index] | busy_phy_map; + for (i = 0; i <= 0x1f; i++, phy_map >>= 1) { + if ((phy_map & 0x1) == 0) { + int val = emac_phy_read(ndev, i, MII_BMCR); + if (val != 0xffff && val != -1) + break; + } + } + if (i == 0x20) { + printk(KERN_WARNING "emac%d: Can't find PHY.\n", ocpdev->def->index); + rc = -ENODEV; + goto bail; + } + busy_phy_map |= 1 << i; + ep->mii_phy_addr = i; + rc = mii_phy_probe(&ep->phy_mii, i); + if (rc) { + printk(KERN_WARNING "emac%d: Failed to probe PHY type.\n", ocpdev->def->index); + rc = -ENODEV; + goto bail; + } + + /* Setup initial PHY config & startup aneg */ + if (ep->phy_mii.def->ops->init) + ep->phy_mii.def->ops->init(&ep->phy_mii); + netif_carrier_off(ndev); + if (ep->phy_mii.def->features & SUPPORTED_Autoneg) + ep->want_autoneg = 1; + emac_start_link(ep, NULL); + + + /* read the MAC Address */ + bd = (bd_t *) __res; + for (i = 0; i < 6; i++) + ndev->dev_addr[i] = bd->BD_EMAC_ADDR(ocpdev->def->index, i); /* Marco to disques array */ + + /* Fill in the driver function table */ + ndev->open = &emac_open; + ndev->hard_start_xmit = &emac_start_xmit; + ndev->stop = &emac_close; + ndev->get_stats = &emac_stats; + ndev->set_multicast_list = &emac_set_multicast_list; + ndev->do_ioctl = &emac_ioctl; + + SET_MODULE_OWNER(ndev); + + rc = register_netdev(ndev); + if (rc != 0) + goto bail; + + printk("%s: IBM emac, MAC %02x:%02x:%02x:%02x:%02x:%02x\n", + ndev->name, + ndev->dev_addr[0], ndev->dev_addr[1], ndev->dev_addr[2], + ndev->dev_addr[3], ndev->dev_addr[4], ndev->dev_addr[5]); + printk(KERN_INFO "%s: Found %s PHY (0x%02x)\n", + ndev->name, ep->phy_mii.def->name, ep->mii_phy_addr); + + +bail: + if (rc && commac_reg) + mal_unregister_commac(ep->mal, &ep->commac); + if (rc && ndev) + kfree(ndev); + + return rc; + +} + +/* Structure for a device driver */ +static struct ocp_device_id emac_ids[] = +{ + { .vendor = OCP_ANY_ID, .function = OCP_FUNC_EMAC }, + { .vendor = OCP_VENDOR_INVALID } +}; + +static struct ocp_driver emac_driver = +{ + .name = "emac", + .id_table = emac_ids, + + .probe = emac_probe, + .remove = emac_remove, +}; + +static int __init +emac_init(void) +{ + int rc; + + printk(KERN_INFO DRV_NAME ": " DRV_DESC ", version " DRV_VERSION "\n"); + printk(KERN_INFO "Maintained by " DRV_AUTHOR "\n"); + + if (skb_res > 2) { + printk(KERN_WARNING "Invalid skb_res: %d, cropping to 2\n", skb_res); + skb_res = 2; + } + rc = ocp_register_driver(&emac_driver); + if (rc == 0) { + ocp_unregister_driver(&emac_driver); + return -ENODEV; + } + + return 0; +} + + + +static void __exit +emac_exit(void) +{ + ocp_unregister_driver(&emac_driver); +} + +module_init(emac_init); +module_exit(emac_exit); diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_enet.h cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_enet.h --- cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_enet.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_enet.h 2004-11-02 17:41:19.000000000 +0900 @@ -0,0 +1,160 @@ +/* + * ibm_ocp_enet.h + * + * Ethernet driver for the built in ethernet on the IBM 405 PowerPC + * processor. + * + * Armin Kuster akuster@mvista.com + * Sept, 2001 + * + * Orignial driver + * Johnnie Peters + * jpeters@mvista.com + * + * Copyright 2000 MontaVista Softare Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Version: 1.0: Name change - armin + * Version: 1.0: Added extern prototypes for new mal func. - David M. + * : removed #ifdef for irqs.i - Armin + * : added irq_resourse to private data struct. + * + * Version: 1.1: Added new min/max value for phy & removed unused phy_id_done - * - andrew May + * Version: 1.2: added all emac extern protos here - Armin + * + * Version: 1.3: Using CONFIG_IBM_OCP_ZMII instead of ZMII_NUMS > 0 + * + * Version: 1.3: Name change *_driver to *_dev + * Version: 1.4: removed irq_resource & BL_* defines + * + */ + +#ifndef _IBM_OCP_ENET_H_ +#define _IBM_OCP_ENET_H_ + +#include +#include +#include /* For phys_addr_t */ + +#include "ibm_emac.h" +#include "ibm_ocp_phy.h" +#include "ibm_ocp_zmii.h" +#include "ibm_ocp_mal.h" + +#ifndef CONFIG_IBM_OCP_ENET_TX_BUFF +#define NUM_TX_BUFF 64 +#define NUM_RX_BUFF 64 +#else +#define NUM_TX_BUFF CONFIG_IBM_OCP_ENET_TX_BUFF +#define NUM_RX_BUFF CONFIG_IBM_OCP_ENET_RX_BUFF +#endif + +/* This does 16 byte alignment, exactly what we need. + * The packet length includes FCS, but we don't want to + * include that when passing upstream as it messes up + * bridging applications. + */ +#ifndef CONFIG_IBM_OCP_ENET_SKB_RES +#define SKB_RES 2 +#else +#define SKB_RES CONFIG_IBM_OCP_ENET_SKB_RES +#endif + +/* Note about alignement. alloc_skb() returns a cache line + * aligned buffer. However, dev_alloc_skb() will add 16 more + * bytes and "reserve" them, so our buffer will actually end + * on a half cache line. What we do is to use directly + * alloc_skb, allocate 16 more bytes to match the total amount + * allocated by dev_alloc_skb(), but we don't reserve. + */ +#define MAX_NUM_BUF_DESC 255 +#define DESC_RX_BUF_SIZE 1536 +#define DESC_BUF_SIZE_REG (DESC_RX_BUF_SIZE / 16) + +/* Transmitter timeout. */ +#define TX_TIMEOUT (2*HZ) +#define OCP_RESET_DELAY 50 +#define MDIO_DELAY 2 + +/* Power managment shift registers */ +#define IBM_CPM_EMMII 0 /* Shift value for MII */ +#define IBM_CPM_EMRX 1 /* Shift value for recv */ +#define IBM_CPM_EMTX 2 /* Shift value for MAC */ +#define IBM_CPM_EMAC(x) (((x)>>IBM_CPM_EMMII) | ((x)>>IBM_CPM_EMRX) | ((x)>>IBM_CPM_EMTX)) + +#ifdef CONFIG_IBM_OCP_ENET_ERROR_MSG +void emac_serr_dump_0(struct net_device *dev); +void emac_serr_dump_1(struct net_device *dev); +void emac_err_dump(struct net_device *dev, int em0isr); +void emac_phy_dump(struct net_device *); +void emac_desc_dump(struct net_device *); +void emac_mac_dump(struct net_device *); +void emac_mal_dump(struct net_device *); +#else +#define emac_serr_dump_0(dev) do { } while (0) +#define emac_serr_dump_1(dev) do { } while (0) +#define emac_err_dump(dev,x) do { } while (0) +#define emac_phy_dump(dev) do { } while (0) +#define emac_desc_dump(dev) do { } while (0) +#define emac_mac_dump(dev) do { } while (0) +#define emac_mal_dump(dev) do { } while (0) +#endif + + +struct ocp_enet_private { + struct sk_buff *tx_skb[NUM_TX_BUFF]; + struct sk_buff *rx_skb[NUM_RX_BUFF]; + struct mal_descriptor *tx_desc; + struct mal_descriptor *rx_desc; + struct mal_descriptor *rx_dirty; + struct net_device_stats stats; + int tx_cnt; + int rx_slot; + int dirty_rx; + int tx_slot; + int ack_slot; + + struct mii_phy phy_mii; + int mii_phy_addr; + int want_autoneg; + int timer_ticks; + struct timer_list link_timer; + struct net_device *mdio_dev; + + struct ocp_device *zmii_dev; + int zmii_input; + + struct ibm_ocp_mal *mal; + int mal_tx_chan, mal_rx_chan; + struct mal_commac commac; + + int opened; + int going_away; + int wol_irq; + volatile emac_t *emacp; + struct ocp_device *ocpdev; + struct net_device *ndev; + spinlock_t lock; +}; + + +#endif /* _IBM_OCP_ENET_H_ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_mal.c cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_mal.c --- cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_mal.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_mal.c 2004-11-02 12:57:39.000000000 +0900 @@ -0,0 +1,484 @@ +/* + * ibm_ocp_mal.c + * + * Armin Kuster akuster@mvista.com + * Juen, 2002 + * + * Copyright 2002 MontaVista Softare Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * TODO: Move to a separate module + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "ibm_ocp_mal.h" + +// Locking: Should we share a lock with the client ? The client could provide +// a lock pointer (optionally) in the commac structure... I don't think this is +// really necessary though + + +/* This lock protects the commac list. On today UP implementations, it's + * really only used as IRQ protection in mal_{register,unregister}_commac() + */ +static rwlock_t mal_list_lock = RW_LOCK_UNLOCKED; + +int +mal_register_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac) +{ + unsigned long flags; + + write_lock_irqsave(&mal_list_lock, flags); + + /* Don't let multiple commacs claim the same channel */ + if ( (mal->tx_chan_mask & commac->tx_chan_mask) || + (mal->rx_chan_mask & commac->rx_chan_mask) ) { + write_unlock_irqrestore(&mal_list_lock, flags); + return -EBUSY; + } + + mal->tx_chan_mask |= commac->tx_chan_mask; + mal->rx_chan_mask |= commac->rx_chan_mask; + + list_add(&commac->list, &mal->commac); + + write_unlock_irqrestore(&mal_list_lock, flags); + + MOD_INC_USE_COUNT; + + return 0; +} + +int +mal_unregister_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac) +{ + unsigned long flags; + + write_lock_irqsave(&mal_list_lock, flags); + + mal->tx_chan_mask &= ~commac->tx_chan_mask; + mal->rx_chan_mask &= ~commac->rx_chan_mask; + + list_del_init(&commac->list); + + write_unlock_irqrestore(&mal_list_lock, flags); + + MOD_DEC_USE_COUNT; + + return 0; +} + +int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, unsigned long size) +{ + switch (channel) { + case 0: + set_mal_dcrn(mal, DCRN_MALRCBS0, size); + break; +#ifdef DCRN_MALRCBS1 + case 1: + set_mal_dcrn(mal, DCRN_MALRCBS1, size); + break; +#endif +#ifdef DCRN_MALRCBS2 + case 2: + set_mal_dcrn(mal, DCRN_MALRCBS2, size); + break; +#endif +#ifdef DCRN_MALRCBS3 + case 3: + set_mal_dcrn(mal, DCRN_MALRCBS3, size); + break; +#endif + default: + return -EINVAL; + } + + return 0; +} + +static void +mal_serr(int irq, void *dev_instance, struct pt_regs *regs) +{ + struct ibm_ocp_mal *mal = dev_instance; + unsigned long mal_error; + + /* + * This SERR applies to one of the devices on the MAL, here we charge + * it against the first EMAC registered for the MAL. + */ + + mal_error = get_mal_dcrn(mal, DCRN_MALESR); + + printk(KERN_ERR "%s: System Error (MALESR=%lx)\n", + "MAL" /* FIXME: get the name right */, mal_error); + + /* FIXME: decipher error */ + /* DIXME: distribute to commacs, if possible */ + + /* Clear the error status register */ + set_mal_dcrn(mal, DCRN_MALESR, mal_error); +} + +static void +mal_txeob(int irq, void *dev_instance, struct pt_regs *regs) +{ + struct ibm_ocp_mal *mal = dev_instance; + struct list_head *l; + unsigned long isr; + + isr = get_mal_dcrn(mal, DCRN_MALTXEOBISR); + set_mal_dcrn(mal, DCRN_MALTXEOBISR, isr); + + read_lock(&mal_list_lock); + list_for_each(l, &mal->commac) { + struct mal_commac *mc = list_entry(l, struct mal_commac, list); + + if (isr & mc->tx_chan_mask) { + mc->ops->txeob(mc->dev, isr & mc->tx_chan_mask); + } + } + read_unlock(&mal_list_lock); +} + +static void +mal_rxeob(int irq, void *dev_instance, struct pt_regs *regs) +{ + struct ibm_ocp_mal *mal = dev_instance; + struct list_head *l; + unsigned long isr; + + + isr = get_mal_dcrn(mal, DCRN_MALRXEOBISR); + set_mal_dcrn(mal, DCRN_MALRXEOBISR, isr); + + read_lock(&mal_list_lock); + list_for_each(l, &mal->commac) { + struct mal_commac *mc = list_entry(l, struct mal_commac, list); + + if (isr & mc->rx_chan_mask) { + mc->ops->rxeob(mc->dev, isr & mc->rx_chan_mask); + } + } + read_unlock(&mal_list_lock); +} + +static void +mal_txde(int irq, void *dev_instance, struct pt_regs *regs) +{ + struct ibm_ocp_mal *mal = dev_instance; + struct list_head *l; + unsigned long deir; + + deir = get_mal_dcrn(mal, DCRN_MALTXDEIR); + + /* FIXME: print which MAL correctly */ + printk(KERN_WARNING "%s: Tx descriptor error (MALTXDEIR=%lx)\n", + "MAL", deir); + + read_lock(&mal_list_lock); + list_for_each(l, &mal->commac) { + struct mal_commac *mc = list_entry(l, struct mal_commac, list); + + if (deir & mc->tx_chan_mask) { + mc->ops->txde(mc->dev, deir & mc->tx_chan_mask); + } + } + read_unlock(&mal_list_lock); +} + +/* + * This interrupt should be very rare at best. This occurs when + * the hardware has a problem with the receive descriptors. The manual + * states that it occurs when the hardware cannot the receive descriptor + * empty bit is not set. The recovery mechanism will be to + * traverse through the descriptors, handle any that are marked to be + * handled and reinitialize each along the way. At that point the driver + * will be restarted. + */ +static void +mal_rxde(int irq, void *dev_instance, struct pt_regs *regs) +{ + struct ibm_ocp_mal *mal = dev_instance; + struct list_head *l; + unsigned long deir; + + deir = get_mal_dcrn(mal, DCRN_MALRXDEIR); + + /* + * This really is needed. This case encountered in stress testing. + */ + if (deir == 0) + return; + + /* FIXME: print which MAL correctly */ + printk(KERN_WARNING "%s: Rx descriptor error (MALRXDEIR=%lx)\n", + "MAL", deir); + + read_lock(&mal_list_lock); + list_for_each(l, &mal->commac) { + struct mal_commac *mc = list_entry(l, struct mal_commac, list); + + if (deir & mc->rx_chan_mask) { + mc->ops->rxde(mc->dev, deir & mc->rx_chan_mask); + } + } + read_unlock(&mal_list_lock); +} + +static int __init +mal_probe(struct ocp_device *ocpdev) +{ + struct ibm_ocp_mal *mal = NULL; + struct ocp_func_mal_data *maldata; + int err = 0; + + maldata = (struct ocp_func_mal_data *)ocpdev->def->additions; + if (maldata == NULL) { + printk(KERN_ERR "mal%d: Missing additional datas !\n", ocpdev->def->index); + return -ENODEV; + } + + mal = kmalloc(sizeof(struct ibm_ocp_mal), GFP_KERNEL); + if (mal == NULL) { + printk(KERN_ERR "mal%d: Out of memory allocating MAL structure !\n", + ocpdev->def->index); + return -ENOMEM; + } + memset(mal, 0, sizeof(*mal)); + + switch (ocpdev->def->index) { + case 0: + mal->dcrbase = DCRN_MAL_BASE; + break; +#ifdef DCRN_MAL1_BASE + case 1: + mal->dcrbase = DCRN_MAL1_BASE; + break; +#endif + default: + BUG(); + } + mal->serr_irq = BL_MAL_SERR; + mal->txde_irq = BL_MAL_TXDE; + mal->txeob_irq = BL_MAL_TXEOB; + mal->rxde_irq = BL_MAL_RXDE; + mal->rxeob_irq = BL_MAL_RXEOB; + + mal->num_tx_channels = maldata->num_tx_chans; + mal->num_rx_channels = maldata->num_rx_chans; + + /**************************/ + + INIT_LIST_HEAD(&mal->commac); + + + set_mal_dcrn(mal, DCRN_MALRXCARR, 0xFFFFFFFF); + set_mal_dcrn(mal, DCRN_MALTXCARR, 0xFFFFFFFF); + + set_mal_dcrn(mal, DCRN_MALCR, MALCR_MMSR); /* 384 */ + /* FIXME: Add delay */ + + /* Set the MAL configuration register */ + set_mal_dcrn(mal, DCRN_MALCR, + MALCR_PLBB | MALCR_OPBBL | MALCR_LEA | + MALCR_PLBLT_DEFAULT); + + /* It would be nice to allocate buffers separately for each + * channel, but we can't because the channels share the upper + * 13 bits of address lines. Each channels buffer must also + * be 4k aligned, so we allocate 4k for each channel. This is + * inefficient FIXME: do better, if possible */ + + mal->tx_virt_addr = consistent_alloc(GFP_KERNEL, + MAL_DT_ALIGN * mal->num_tx_channels, + &mal->tx_phys_addr); + if (mal->tx_virt_addr == NULL) { + printk(KERN_ERR "mal%d: Out of memory allocating MAL descriptors !\n", + ocpdev->def->index); + err = -ENOMEM; + goto fail; + } + + /* God, oh, god, I hate DCRs */ + set_mal_dcrn(mal, DCRN_MALTXCTP0R, mal->tx_phys_addr); +#ifdef DCRN_MALTXCTP1R + if (mal->num_tx_channels > 1) + set_mal_dcrn(mal, DCRN_MALTXCTP1R, + mal->tx_phys_addr + MAL_DT_ALIGN); +#endif /* DCRN_MALTXCTP1R */ +#ifdef DCRN_MALTXCTP2R + if (mal->num_tx_channels > 2) + set_mal_dcrn(mal, DCRN_MALTXCTP2R, + mal->tx_phys_addr + 2*MAL_DT_ALIGN); +#endif /* DCRN_MALTXCTP2R */ +#ifdef DCRN_MALTXCTP3R + if (mal->num_tx_channels > 3) + set_mal_dcrn(mal, DCRN_MALTXCTP3R, + mal->tx_phys_addr + 3*MAL_DT_ALIGN); +#endif /* DCRN_MALTXCTP3R */ +#ifdef DCRN_MALTXCTP4R + if (mal->num_tx_channels > 4) + set_mal_dcrn(mal, DCRN_MALTXCTP4R, + mal->tx_phys_addr + 4*MAL_DT_ALIGN); +#endif /* DCRN_MALTXCTP4R */ +#ifdef DCRN_MALTXCTP5R + if (mal->num_tx_channels > 5) + set_mal_dcrn(mal, DCRN_MALTXCTP5R, + mal->tx_phys_addr + 5*MAL_DT_ALIGN); +#endif /* DCRN_MALTXCTP5R */ +#ifdef DCRN_MALTXCTP6R + if (mal->num_tx_channels > 6) + set_mal_dcrn(mal, DCRN_MALTXCTP6R, + mal->tx_phys_addr + 6*MAL_DT_ALIGN); +#endif /* DCRN_MALTXCTP6R */ +#ifdef DCRN_MALTXCTP7R + if (mal->num_tx_channels > 7) + set_mal_dcrn(mal, DCRN_MALTXCTP7R, + mal->tx_phys_addr + 7*MAL_DT_ALIGN); +#endif /* DCRN_MALTXCTP7R */ + + mal->rx_virt_addr = consistent_alloc(GFP_KERNEL, + MAL_DT_ALIGN * mal->num_rx_channels, + &mal->rx_phys_addr); + + set_mal_dcrn(mal, DCRN_MALRXCTP0R, mal->rx_phys_addr); +#ifdef DCRN_MALRXCTP1R + if (mal->num_rx_channels > 1) + set_mal_dcrn(mal, DCRN_MALRXCTP1R, + mal->rx_phys_addr + MAL_DT_ALIGN); +#endif /* DCRN_MALRXCTP1R */ +#ifdef DCRN_MALRXCTP2R + if (mal->num_rx_channels > 2) + set_mal_dcrn(mal, DCRN_MALRXCTP2R, + mal->rx_phys_addr + 2*MAL_DT_ALIGN); +#endif /* DCRN_MALRXCTP2R */ +#ifdef DCRN_MALRXCTP3R + if (mal->num_rx_channels > 3) + set_mal_dcrn(mal, DCRN_MALRXCTP3R, + mal->rx_phys_addr + 3*MAL_DT_ALIGN); +#endif /* DCRN_MALRXCTP3R */ + + err = request_irq(mal->serr_irq, mal_serr, 0 ,"MAL SERR", mal); + if (err) + goto fail; + err = request_irq(mal->txde_irq, mal_txde,0, "MAL TX DE ", mal); + if (err) + goto fail; + err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal); + if (err) + goto fail; + err = request_irq(mal->rxde_irq, mal_rxde, 0, "MAL RX DE", mal); + if (err) + goto fail; + err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal); + if (err) + goto fail; + + set_mal_dcrn(mal, DCRN_MALIER, + MALIER_DE | MALIER_NE | MALIER_TE | + MALIER_OPBE | MALIER_PLBE); + + /* Advertise me to the rest of the world */ + ocp_set_drvdata(ocpdev, mal); + + printk(KERN_INFO "mal%d: Initialized, %d tx channels, %d rx channels\n", + ocpdev->def->index, mal->num_tx_channels, mal->num_rx_channels); + + return 0; + + fail: + /* FIXME: dispose requested IRQs ! */ + if (err && mal) + kfree(mal); + return err; +} + +static void __exit +mal_remove(struct ocp_device *ocpdev) +{ + struct ibm_ocp_mal *mal = ocp_get_drvdata(ocpdev); + + ocp_set_drvdata(ocpdev, NULL); + + /* FIXME: shut down the MAL, deal with dependency with emac */ + free_irq(mal->serr_irq, mal); + free_irq(mal->txde_irq, mal); + free_irq(mal->txeob_irq, mal); + free_irq(mal->rxde_irq, mal); + free_irq(mal->rxeob_irq, mal); + + if (mal->tx_virt_addr) + consistent_free(mal->tx_virt_addr); + if (mal->rx_virt_addr) + consistent_free(mal->rx_virt_addr); + + kfree(mal); +} + +/* Structure for a device driver */ +static struct ocp_device_id mal_ids[] = +{ + { .vendor = OCP_ANY_ID, .function = OCP_FUNC_MAL }, + { .vendor = OCP_VENDOR_INVALID } +}; + +static struct ocp_driver mal_driver = +{ + .name = "mal", + .id_table = mal_ids, + + .probe = mal_probe, + .remove = mal_remove, +}; + +static int __init +init_mals(void) +{ + int rc; + + rc = ocp_register_driver(&mal_driver); + if (rc == 0) { + ocp_unregister_driver(&mal_driver); + return -ENODEV; + } + + return 0; +} + +static void __exit +exit_mals(void) +{ + ocp_unregister_driver(&mal_driver); +} + +module_init(init_mals); +module_exit(exit_mals); diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_mal.h cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_mal.h --- cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_mal.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_mal.h 2004-11-02 17:41:19.000000000 +0900 @@ -0,0 +1,147 @@ +/* + * 06/02/02 -Armin + * added new mal functions and defines from ibm_ocp_enet.h + */ + +#ifndef _IBM_OCP_MAL_H +#define _IBM_OCP_MAL_H + +#include + +#define MAL_DT_ALIGN (4096) /* Alignment for each channel's descriptor table */ + +#define MAL_CHAN_MASK(chan) (0x80000000 >> (chan)) + +/* MAL Buffer Descriptor structure */ +struct mal_descriptor { + volatile unsigned short ctrl; /* MAL / Commac status control bits */ + volatile short data_len; /* Max length is 4K-1 (12 bits) */ + unsigned char *data_ptr; /* pointer to actual data buffer */ +} __attribute__((packed)); + +/* the following defines are for the MadMAL status and control registers. */ +/* MADMAL transmit and receive status/control bits */ +#define MAL_RX_CTRL_EMPTY 0x8000 +#define MAL_RX_CTRL_WRAP 0x4000 +#define MAL_RX_CTRL_CM 0x2000 +#define MAL_RX_CTRL_LAST 0x1000 +#define MAL_RX_CTRL_FIRST 0x0800 +#define MAL_RX_CTRL_INTR 0x0400 + +#define MAL_TX_CTRL_READY 0x8000 +#define MAL_TX_CTRL_WRAP 0x4000 +#define MAL_TX_CTRL_CM 0x2000 +#define MAL_TX_CTRL_LAST 0x1000 +#define MAL_TX_CTRL_INTR 0x0400 + +struct mal_commac_ops { + void (*txeob)(void *dev, u32 chanmask); + void (*txde)(void *dev, u32 chanmask); + void (*rxeob)(void *dev, u32 chanmask); + void (*rxde)(void *dev, u32 chanmask); +}; + +struct mal_commac { + struct mal_commac_ops *ops; + void *dev; + u32 tx_chan_mask, rx_chan_mask; + struct list_head list; +}; + +/* FIXME: Work this out better */ +#define MAL_MAX_TX_CHANNELS (EMAC_NUMS*2) +#define MAL_MAX_RX_CHANNELS (EMAC_NUMS) + +struct ibm_ocp_mal { + int dcrbase; + int serr_irq, txeob_irq, txde_irq, rxeob_irq, rxde_irq; + + struct list_head commac; + u32 tx_chan_mask, rx_chan_mask; + + int num_tx_channels; + dma_addr_t tx_phys_addr; + struct mal_descriptor *tx_virt_addr; + + int num_rx_channels; + dma_addr_t rx_phys_addr; + struct mal_descriptor *rx_virt_addr; +}; + +#ifdef DCRN_MAL1_BASE +#define NUM_MALS 2 +#else +#define NUM_MALS 1 +#endif + +extern struct ibm_ocp_mal mal_table[NUM_MALS]; + +#define GET_MAL_STANZA(base,dcrn) \ + case base: \ + x = mfdcr(dcrn(base)); \ + break; + +#define SET_MAL_STANZA(base,dcrn, val) \ + case base: \ + mtdcr(dcrn(base), (val)); \ + break; + +#define GET_MAL0_STANZA(dcrn) GET_MAL_STANZA(DCRN_MAL_BASE,dcrn) +#define SET_MAL0_STANZA(dcrn,val) SET_MAL_STANZA(DCRN_MAL_BASE,dcrn,val) + +#ifdef DCRN_MAL1_BASE +#define GET_MAL1_STANZA(dcrn) GET_MAL_STANZA(DCRN_MAL1_BASE,dcrn) +#define SET_MAL1_STANZA(dcrn,val) SET_MAL_STANZA(DCRN_MAL1_BASE,dcrn,val) +#else /* ! DCRN_MAL1_BASE */ +#define GET_MAL1_STANZA(dcrn) +#define SET_MAL1_STANZA(dcrn,val) +#endif + + +#define get_mal_dcrn(mal, dcrn) ({ \ + u32 x; \ + switch ((mal)->dcrbase) { \ + GET_MAL0_STANZA(dcrn) \ + GET_MAL1_STANZA(dcrn) \ + default: \ + BUG(); \ + } \ +x; }) + +#define set_mal_dcrn(mal, dcrn, val) do { \ + switch ((mal)->dcrbase) { \ + SET_MAL0_STANZA(dcrn,val) \ + SET_MAL1_STANZA(dcrn,val) \ + default: \ + BUG(); \ + } } while (0) + + +static inline void mal_enable_tx_channels(struct ibm_ocp_mal *mal, u32 chanmask) +{ + set_mal_dcrn(mal, DCRN_MALTXCASR, + get_mal_dcrn(mal, DCRN_MALTXCASR) | chanmask); +} + +static inline void mal_disable_tx_channels(struct ibm_ocp_mal *mal, u32 chanmask) +{ + set_mal_dcrn(mal, DCRN_MALTXCARR, chanmask); +} + +static inline void mal_enable_rx_channels(struct ibm_ocp_mal *mal, u32 chanmask) +{ + set_mal_dcrn(mal, DCRN_MALRXCASR, + get_mal_dcrn(mal, DCRN_MALRXCASR) | chanmask); +} + +static inline void mal_disable_rx_channels(struct ibm_ocp_mal *mal, u32 chanmask) +{ + set_mal_dcrn(mal, DCRN_MALRXCARR, chanmask); +} + +extern int mal_register_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac); +extern int mal_unregister_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac); + +extern int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, unsigned long size); + +#endif /* _IBM_OCP_MAL_H */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_phy.c cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_phy.c --- cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_phy.c 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_phy.c 2004-11-01 22:35:10.000000000 +0900 @@ -0,0 +1,243 @@ +/* + * ibm_ocp_phy.c + * + * PHY drivers for the ibm ocp ethernet driver. Borrowed + * from sungem_phy.c, though I only kept the generic MII + * driver for now. + * + * This file should be shared with other drivers or eventually + * merged as the "low level" part of miilib + * + * (c) 2003, Benjamin Herrenscmidt (benh@kernel.crashing.org) + * + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ibm_ocp_phy.h" + + +static inline int __phy_read(struct mii_phy* phy, int id, int reg) +{ + return phy->mdio_read(phy->dev, id, reg); +} + +static inline void __phy_write(struct mii_phy* phy, int id, int reg, int val) +{ + phy->mdio_write(phy->dev, id, reg, val); +} + +static inline int phy_read(struct mii_phy* phy, int reg) +{ + return phy->mdio_read(phy->dev, phy->mii_id, reg); +} + +static inline void phy_write(struct mii_phy* phy, int reg, int val) +{ + phy->mdio_write(phy->dev, phy->mii_id, reg, val); +} + +static int reset_one_mii_phy(struct mii_phy* phy, int phy_id) +{ + u16 val; + int limit = 10000; + + val = __phy_read(phy, phy_id, MII_BMCR); + val &= ~BMCR_ISOLATE; + val |= BMCR_RESET; + __phy_write(phy, phy_id, MII_BMCR, val); + + udelay(100); + + while (limit--) { + val = __phy_read(phy, phy_id, MII_BMCR); + if ((val & BMCR_RESET) == 0) + break; + udelay(10); + } + if ((val & BMCR_ISOLATE) && limit > 0) + __phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE); + + return (limit <= 0); +} + +static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise) +{ + u16 ctl, adv; + + phy->autoneg = 1; + phy->speed = SPEED_10; + phy->duplex = DUPLEX_HALF; + phy->pause = 0; + phy->advertising = advertise; + + /* Setup standard advertise */ + adv = phy_read(phy, MII_ADVERTISE); + adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); + if (advertise & ADVERTISED_10baseT_Half) + adv |= ADVERTISE_10HALF; + if (advertise & ADVERTISED_10baseT_Full) + adv |= ADVERTISE_10FULL; + if (advertise & ADVERTISED_100baseT_Half) + adv |= ADVERTISE_100HALF; + if (advertise & ADVERTISED_100baseT_Full) + adv |= ADVERTISE_100FULL; + phy_write(phy, MII_ADVERTISE, adv); + + /* Start/Restart aneg */ + ctl = phy_read(phy, MII_BMCR); + ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); + phy_write(phy, MII_BMCR, ctl); + + return 0; +} + +static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd) +{ + u16 ctl; + + phy->autoneg = 0; + phy->speed = speed; + phy->duplex = fd; + phy->pause = 0; + + ctl = phy_read(phy, MII_BMCR); + ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_ANENABLE); + + /* First reset the PHY */ + phy_write(phy, MII_BMCR, ctl | BMCR_RESET); + + /* Select speed & duplex */ + switch(speed) { + case SPEED_10: + break; + case SPEED_100: + ctl |= BMCR_SPEED100; + break; + case SPEED_1000: + default: + return -EINVAL; + } + if (fd == DUPLEX_FULL) + ctl |= BMCR_FULLDPLX; + phy_write(phy, MII_BMCR, ctl); + + return 0; +} + +static int genmii_poll_link(struct mii_phy *phy) +{ + u16 status; + + (void)phy_read(phy, MII_BMSR); + status = phy_read(phy, MII_BMSR); + if ((status & BMSR_LSTATUS) == 0) + return 0; + if (phy->autoneg && !(status & BMSR_ANEGCOMPLETE)) + return 0; + return 1; +} + +static int genmii_read_link(struct mii_phy *phy) +{ + u16 lpa; + + if (phy->autoneg) { + lpa = phy_read(phy, MII_LPA); + + if (lpa & (LPA_10FULL | LPA_100FULL)) + phy->duplex = DUPLEX_FULL; + else + phy->duplex = DUPLEX_HALF; + if (lpa & (LPA_100FULL | LPA_100HALF)) + phy->speed = SPEED_100; + else + phy->speed = SPEED_10; + phy->pause = 0; + } + /* On non-aneg, we assume what we put in BMCR is the speed, + * though magic-aneg shouldn't prevent this case from occurring + */ + + return 0; +} + + +#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \ + SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \ + SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII) +#define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \ + SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full) + + +/* Generic implementation for most 10/100 PHYs */ +static struct mii_phy_ops generic_phy_ops = { + setup_aneg: genmii_setup_aneg, + setup_forced: genmii_setup_forced, + poll_link: genmii_poll_link, + read_link: genmii_read_link +}; + +static struct mii_phy_def genmii_phy_def = { + phy_id: 0x00000000, + phy_id_mask: 0x00000000, + name: "Generic MII", + features: MII_BASIC_FEATURES, + magic_aneg: 0, + ops: &generic_phy_ops +}; + +static struct mii_phy_def* mii_phy_table[] = { + &genmii_phy_def, + NULL +}; + +int mii_phy_probe(struct mii_phy *phy, int mii_id) +{ + int rc; + u32 id; + struct mii_phy_def* def; + int i; + + phy->autoneg = 0; + phy->advertising = 0; + phy->mii_id = mii_id; + phy->speed = 0; + phy->duplex = 0; + phy->pause = 0; + + /* Take PHY out of isloate mode and reset it. */ + rc = reset_one_mii_phy(phy, mii_id); + if (rc) + return -ENODEV; + + /* Read ID and find matching entry */ + id = (phy_read(phy, MII_PHYSID1) << 16 | phy_read(phy, MII_PHYSID2)) + & 0xfffffff0; + for (i=0; (def = mii_phy_table[i]) != NULL; i++) + if ((id & def->phy_id_mask) == def->phy_id) + break; + /* Should never be NULL (we have a generic entry), but... */ + if (def == NULL) + return -ENODEV; + + phy->def = def; + + /* Setup default advertising */ + phy->advertising = def->features; + + return 0; +} + +MODULE_LICENSE("GPL"); diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_phy.h cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_phy.h --- cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_phy.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_phy.h 2004-11-01 22:35:10.000000000 +0900 @@ -0,0 +1,90 @@ + +/* + * ibm_ocp_phy.h + * + * + * Benjamin Herrenschmidt + * February 2003 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * This file basically duplicates sungem_phy.{c,h} with different PHYs + * supported. I'm looking into merging that in a single mii layer more + * flexible than mii.c + */ + +#ifndef _IBM_OCP_PHY_H_ +#define _IBM_OCP_PHY_H_ + +struct mii_phy; + +/* Operations supported by any kind of PHY */ +struct mii_phy_ops +{ + int (*init)(struct mii_phy *phy); + int (*suspend)(struct mii_phy *phy, int wol_options); + int (*setup_aneg)(struct mii_phy *phy, u32 advertise); + int (*setup_forced)(struct mii_phy *phy, int speed, int fd); + int (*poll_link)(struct mii_phy *phy); + int (*read_link)(struct mii_phy *phy); +}; + +/* Structure used to statically define an mii/gii based PHY */ +struct mii_phy_def +{ + u32 phy_id; /* Concatenated ID1 << 16 | ID2 */ + u32 phy_id_mask; /* Significant bits */ + u32 features; /* Ethtool SUPPORTED_* defines */ + int magic_aneg; /* Autoneg does all speed test for us */ + const char* name; + const struct mii_phy_ops* ops; +}; + +/* An instance of a PHY, partially borrowed from mii_if_info */ +struct mii_phy +{ + struct mii_phy_def* def; + int advertising; + int mii_id; + + /* 1: autoneg enabled, 0: disabled */ + int autoneg; + + /* forced speed & duplex (no autoneg) + * partner speed & duplex & pause (autoneg) + */ + int speed; + int duplex; + int pause; + + /* Provided by host chip */ + struct net_device* dev; + int (*mdio_read) (struct net_device *dev, int mii_id, int reg); + void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val); +}; + +/* Pass in a struct mii_phy with dev, mdio_read and mdio_write + * filled, the remaining fields will be filled on return + */ +extern int mii_phy_probe(struct mii_phy *phy, int mii_id); + +#endif /* _IBM_OCP_PHY_H_ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_zmii.h cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_zmii.h --- cset-v2.4.20~/drivers/net/ibm_emac/ibm_ocp_zmii.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/drivers/net/ibm_emac/ibm_ocp_zmii.h 2004-11-01 22:35:10.000000000 +0900 @@ -0,0 +1,109 @@ +/* + * ocp_zmii.h + * + * Defines for the IBM ZMII bridge + * + * Armin Kuster akuster@mvista.com + * Dec, 2001 + * + * Copyright 2001 MontaVista Softare Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * V 1.2 (04/19/02 ) - Armin + * added support for emac 2 & 3 + */ + +#ifndef _OCP_ZMII_H_ +#define _OCP_ZMII_H_ + +#include + +/* ZMII bridge registers */ +struct zmii_regs { + u32 fer; /* Function enable reg */ + u32 ssr; /* Spedd select reg */ + u32 smiirs; /* SMII status reg */ +}; + +/* ZMII device */ +struct ibm_ocp_zmii { + struct zmii_regs *base; + int mode; + int users;/* number of EMACs using this ZMII bridge */ +}; + +/* Fuctional Enable Reg */ + +#define ZMII_MDI0 0x80000000 +#define ZMII_SMII0 0x40000000 +#define ZMII_RMII0 0x20000000 +#define ZMII_MII0 0x10000000 +#define ZMII_MDI1 0x08000000 +#define ZMII_SMII1 0x04000000 +#define ZMII_RMII1 0x02000000 +#define ZMII_MII1 0x01000000 +#define ZMII_MDI2 0x00800000 +#define ZMII_SMII2 0x00400000 +#define ZMII_RMII2 0x00200000 +#define ZMII_MII2 0x00100000 +#define ZMII_MDI3 0x00080000 +#define ZMII_SMII3 0x00040000 +#define ZMII_RMII3 0x00020000 +#define ZMII_MII3 0x00010000 + +/* Speed Selection reg */ + +#define ZMII_SCI0 0x40000000 +#define ZMII_FSS0 0x20000000 +#define ZMII_SP0 0x10000000 +#define ZMII_SCI1 0x04000000 +#define ZMII_FSS1 0x02000000 +#define ZMII_SP1 0x01000000 +#define ZMII_SCI2 0x00400000 +#define ZMII_FSS2 0x00200000 +#define ZMII_SP2 0x00100000 +#define ZMII_SCI3 0x00040000 +#define ZMII_FSS3 0x00020000 +#define ZMII_SP3 0x00010000 + +#define ZMII_MII0_100MB ZMII_SP0 +#define ZMII_MII0_10MB ~ZMII_SP0 +#define ZMII_MII1_100MB ZMII_SP1 +#define ZMII_MII1_10MB ~ZMII_SP1 +#define ZMII_MII2_100MB ZMII_SP2 +#define ZMII_MII2_10MB ~ZMII_SP2 +#define ZMII_MII3_100MB ZMII_SP3 +#define ZMII_MII3_10MB ~ZMII_SP3 + +/* SMII Status reg */ + +#define ZMII_STS0 0xFF000000 /* EMAC0 smii status mask */ +#define ZMII_STS1 0x00FF0000 /* EMAC1 smii status mask */ + + +#define SMII 0 +#define RMII 1 +#define MII 2 +#define MDI 3 +#define ZMII_AUTO 4 + +#endif /* _OCP_ZMII_H_ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/ibm44x.h cset-v2.4.20/include/asm-ppc/ibm44x.h --- cset-v2.4.20~/include/asm-ppc/ibm44x.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/ibm44x.h 2004-11-02 17:38:17.000000000 +0900 @@ -0,0 +1,534 @@ +/* + * include/asm-ppc/ibm44x.h + * + * PPC44x definitions + * + * Matt Porter + * Copyright 2002-2003 MontaVista Software Inc. + * + * Eugene Surovegin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifdef __KERNEL__ +#ifndef __ASM_IBM44x_H__ +#define __ASM_IBM44x_H__ + +#include + +#ifndef __ASSEMBLY__ +/* + * Data structure defining board information maintained by the boot + * ROM on IBM's "Ebony" evaluation board. An effort has been made to + * keep the field names consistent with the 8xx 'bd_t' board info + * structures. + * + * Ebony firmware stores MAC addresses in the F/W VPD area. The + * firmware must store the other dynamic values in NVRAM like on + * the previous 40x systems so they should be accessible if we + * really want them. + */ +typedef struct board_info { + unsigned char bi_enetaddr[2][6]; /* EMAC addresses */ + unsigned int bi_opb_busfreq; /* OPB clock in Hz */ + int bi_iic_fast[2]; /* Use fast i2c mode */ +} bd_t; +#endif /* __ASSEMBLY__ */ + +#ifndef NR_BOARD_IRQS +#define NR_BOARD_IRQS 0 +#endif + +#define _IO_BASE isa_io_base +#define _ISA_MEM_BASE isa_mem_base +#define PCI_DRAM_OFFSET pci_dram_offset + +/* TLB entry offset/size used for pinning kernel lowmem */ +#define PPC44x_PIN_SHIFT 28 +#define PPC44x_PIN_SIZE (1 << PPC44x_PIN_SHIFT) + +/* Lowest TLB slot consumed by the default pinned TLBs */ +#define PPC44x_LOW_SLOT 62 + +/* + * Standard 4GB "page" definitions + */ +#define PPC44x_IO_PAGE 0x0000000100000000ULL +#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL +#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE +#define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL + +/* + * 36-bit trap ranges + */ +#define PPC44x_IO_LO 0x40000000 +#define PPC44x_IO_HI 0x40001000 +#define PPC44x_PCICFG_LO 0x0ec00000 +#define PPC44x_PCICFG_HI 0x0ec7ffff +#define PPC44x_PCIMEM_LO 0x80002000 +#define PPC44x_PCIMEM_HI 0xffffffff + +/* + * The "residual" board information structure the boot loader passes + * into the kernel. + */ +#ifndef __ASSEMBLY__ + +/* + * SPRN definitions + */ +#define SPRN_CPC0_GPIO 0xe5 + +/* + * DCRN definitions + */ + +#ifdef CONFIG_440GX +/* CPRs */ +#define DCRN_CPR_CONFIG_ADDR 0xc +#define DCRN_CPR_CONFIG_DATA 0xd + +#define DCRN_CPR_CLKUPD 0x0020 +#define DCRN_CPR_PLLC 0x0040 +#define DCRN_CPR_PLLD 0x0060 +#define DCRN_CPR_PRIMAD 0x0080 +#define DCRN_CPR_PRIMBD 0x00a0 +#define DCRN_CPR_OPBD 0x00c0 +#define DCRN_CPR_PERD 0x00e0 +#define DCRN_CPR_MALD 0x0100 + +/* CPRs read/write helper macros */ +#define CPR_READ(offset) ({\ + mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ + mfdcr(DCRN_CPR_CONFIG_DATA);}) +#define CPR_WRITE(offset, data) ({\ + mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ + mtdcr(DCRN_CPR_CONFIG_DATA, data);}) + +/* SDRs */ +#define DCRN_SDR_CONFIG_ADDR 0xe +#define DCRN_SDR_CONFIG_DATA 0xf +#define DCRN_SDR_PFC0 0x4100 +#define DCRN_SDR_PFC1 0x4101 +#define DCRN_SDR_MFR 0x4300 +#define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */ +#define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */ +#define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */ +#define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */ +#define DCRN_SDR_MFR_T0TXFL 0x00080000 +#define DCRN_SDR_MFR_T0TXFH 0x00040000 +#define DCRN_SDR_MFR_T1TXFL 0x00020000 +#define DCRN_SDR_MFR_T1TXFH 0x00010000 +#define DCRN_SDR_MFR_E0TXFL 0x00008000 +#define DCRN_SDR_MFR_E0TXFH 0x00004000 +#define DCRN_SDR_MFR_E0RXFL 0x00002000 +#define DCRN_SDR_MFR_E0RXFH 0x00001000 +#define DCRN_SDR_MFR_E1TXFL 0x00000800 +#define DCRN_SDR_MFR_E1TXFH 0x00000400 +#define DCRN_SDR_MFR_E1RXFL 0x00000200 +#define DCRN_SDR_MFR_E1RXFH 0x00000100 +#define DCRN_SDR_MFR_E2TXFL 0x00000080 +#define DCRN_SDR_MFR_E2TXFH 0x00000040 +#define DCRN_SDR_MFR_E2RXFL 0x00000020 +#define DCRN_SDR_MFR_E2RXFH 0x00000010 +#define DCRN_SDR_MFR_E3TXFL 0x00000008 +#define DCRN_SDR_MFR_E3TXFH 0x00000004 +#define DCRN_SDR_MFR_E3RXFL 0x00000002 +#define DCRN_SDR_MFR_E3RXFH 0x00000001 +#define DCRN_SDR_UART0 0x0120 +#define DCRN_SDR_UART1 0x0121 + +/* SDR read/write helper macros */ +#define SDR_READ(offset) ({\ + mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ + mfdcr(DCRN_SDR_CONFIG_DATA);}) +#define SDR_WRITE(offset, data) ({\ + mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ + mtdcr(DCRN_SDR_CONFIG_DATA,data);}) +#endif /* CONFIG_440GX */ + +/* Base DCRNs */ +#define DCRN_DMA0_BASE 0x100 +#define DCRN_DMA1_BASE 0x108 +#define DCRN_DMA2_BASE 0x110 +#define DCRN_DMA3_BASE 0x118 +#define DCRN_DMASR_BASE 0x120 +#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ +#define DCRN_MAL_BASE 0x180 + +/* UIC */ +#define DCRN_UIC0_BASE 0xc0 +#define DCRN_UIC1_BASE 0xd0 +#define UIC0 DCRN_UIC0_BASE +#define UIC1 DCRN_UIC1_BASE + +#define DCRN_UIC_SR(base) (base + 0x0) +#define DCRN_UIC_ER(base) (base + 0x2) +#define DCRN_UIC_CR(base) (base + 0x3) +#define DCRN_UIC_PR(base) (base + 0x4) +#define DCRN_UIC_TR(base) (base + 0x5) +#define DCRN_UIC_MSR(base) (base + 0x6) +#define DCRN_UIC_VR(base) (base + 0x7) +#define DCRN_UIC_VCR(base) (base + 0x8) + +#define UIC0_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define UIC0_UIC1CR 31 /* UIC1 critical interrupt */ + +/* 440GP MAL DCRs */ +#define DCRN_MALCR(base) (base + 0x0) /* Configuration */ +#define DCRN_MALESR(base) (base + 0x1) /* Error Status */ +#define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */ +#define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */ +#define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */ +#define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */ +#define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */ +#define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */ +#define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */ +#define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */ +#define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */ +#define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */ +#define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */ +#define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */ +#define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */ +#define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */ +#define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */ +#define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */ +#define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */ + +/* Compatibility DCRN's */ +#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */ +#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */ +#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */ +#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */ +#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */ +#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */ +#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */ +#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */ + + +#define MALCR_MMSR 0x80000000 /* MAL Software reset */ +#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ +#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ +#define MALCR_PLBP_3 0x00C00000 /* highest */ +#define MALCR_GA 0x00200000 /* Guarded Active Bit */ +#define MALCR_OA 0x00100000 /* Ordered Active Bit */ +#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ +#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ +#define MALCR_PLBLT_2 0x00020000 +#define MALCR_PLBLT_3 0x00010000 +#define MALCR_PLBLT_4 0x00008000 +#ifdef CONFIG_440GP +#define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */ +#else +#define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */ +#endif +#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ +#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ +#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ +#define MALCR_LEA 0x00000002 /* Locked Error Active */ +#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ +/* DCRN_MALESR */ +#define MALESR_EVB 0x80000000 /* Error Valid Bit */ +#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ +#define MALESR_DE 0x00100000 /* Descriptor Error */ +#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ +#define MALESR_OTE 0x00040000 /* OPB Timeout Error */ +#define MALESR_OSE 0x00020000 /* OPB Slave Error */ +#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ +#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ +#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ +#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ +#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ +#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ +/* DCRN_MALIER */ +#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ +#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ +#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ +#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ +#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ +/* DCRN_MALTXEOBISR */ +#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ +#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ + +/* 440GP PLB Arbiter DCRs */ +#define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */ +#define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */ +#define DCRN_PLB0_BESR 0x084 /* PLB Error Status */ +#define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */ +#define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */ +#define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */ + +/* 440GP Clock, PM, chip control */ +#define DCRN_CPC0_SR 0x0b0 +#define DCRN_CPC0_ER 0x0b1 +#define DCRN_CPC0_FR 0x0b2 +#define DCRN_CPC0_SYS0 0x0e0 +#define DCRN_CPC0_SYS1 0x0e1 +#define DCRN_CPC0_CUST0 0x0e2 +#define DCRN_CPC0_CUST1 0x0e3 +#define DCRN_CPC0_STRP0 0x0e4 +#define DCRN_CPC0_STRP1 0x0e5 +#define DCRN_CPC0_STRP2 0x0e6 +#define DCRN_CPC0_STRP3 0x0e7 +#define DCRN_CPC0_GPIO 0x0e8 +#define DCRN_CPC0_PLB 0x0e9 +#define DCRN_CPC0_CR1 0x0ea +#define DCRN_CPC0_CR0 0x0eb +#define DCRN_CPC0_MIRQ0 0x0ec +#define DCRN_CPC0_MIRQ1 0x0ed +#define DCRN_CPC0_JTAGID 0x0ef + +/* 440GP DMA controller DCRs */ +#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */ +#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */ +#define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */ +#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */ +#define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */ +#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */ +#define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */ +#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */ + +#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control 1 */ +#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count 1 */ +#define DCRN_DMASAH1 (DCRN_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */ +#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */ +#define DCRN_DMADAH1 (DCRN_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */ +#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */ +#define DCRN_ASGH1 (DCRN_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */ +#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */ + +#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */ +#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */ +#define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */ +#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */ +#define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */ +#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */ +#define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */ +#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */ + +#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */ +#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */ +#define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */ +#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */ +#define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */ +#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */ +#define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */ +#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */ + +#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ +#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ +#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ +#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ + +/* 440GP DRAM controller DCRs */ +#define DCRN_SDRAM0_CFGADDR 0x010 +#define DCRN_SDRAM0_CFGDATA 0x011 + +#define SDRAM0_B0CR 0x40 +#define SDRAM0_B1CR 0x44 +#define SDRAM0_B2CR 0x48 +#define SDRAM0_B3CR 0x4c + +#define SDRAM_CONFIG_BANK_ENABLE 0x00000001 +#define SDRAM_CONFIG_SIZE_MASK 0x000e0000 +#define SDRAM_CONFIG_BANK_SIZE(reg) ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17) +#define SDRAM_CONFIG_SIZE_8M 0x00000001 +#define SDRAM_CONFIG_SIZE_16M 0x00000002 +#define SDRAM_CONFIG_SIZE_32M 0x00000003 +#define SDRAM_CONFIG_SIZE_64M 0x00000004 +#define SDRAM_CONFIG_SIZE_128M 0x00000005 +#define SDRAM_CONFIG_SIZE_256M 0x00000006 +#define SDRAM_CONFIG_SIZE_512M 0x00000007 +#define PPC44x_MEM_SIZE_8M 0x00800000 +#define PPC44x_MEM_SIZE_16M 0x01000000 +#define PPC44x_MEM_SIZE_32M 0x02000000 +#define PPC44x_MEM_SIZE_64M 0x04000000 +#define PPC44x_MEM_SIZE_128M 0x08000000 +#define PPC44x_MEM_SIZE_256M 0x10000000 +#define PPC44x_MEM_SIZE_512M 0x20000000 + +#ifdef CONFIG_440GX +/* Internal SRAM Controller */ +#define DCRN_SRAM0_SB0CR 0x020 +#define DCRN_SRAM0_SB1CR 0x021 +#define DCRN_SRAM0_SB2CR 0x022 +#define DCRN_SRAM0_SB3CR 0x023 +#define SRAM_SBCR_BAS0 0x80000000 +#define SRAM_SBCR_BAS1 0x80010000 +#define SRAM_SBCR_BAS2 0x80020000 +#define SRAM_SBCR_BAS3 0x80030000 +#define SRAM_SBCR_BU_MASK 0x00000180 +#define SRAM_SBCR_BS_64KB 0x00000800 +#define SRAM_SBCR_BU_RO 0x00000080 +#define SRAM_SBCR_BU_RW 0x00000180 +#define DCRN_SRAM0_BEAR 0x024 +#define DCRN_SRAM0_BESR0 0x025 +#define DCRN_SRAM0_BESR1 0x026 +#define DCRN_SRAM0_PMEG 0x027 +#define DCRN_SRAM0_CID 0x028 +#define DCRN_SRAM0_REVID 0x029 +#define DCRN_SRAM0_DPC 0x02a +#define SRAM_DPC_ENABLE 0x80000000 + +/* L2 Cache Controller */ +#define DCRN_L2C0_CFG 0x030 +#define L2C_CFG_L2M 0x80000000 +#define L2C_CFG_ICU 0x40000000 +#define L2C_CFG_DCU 0x20000000 +#define L2C_CFG_DCW_MASK 0x1e000000 +#define L2C_CFG_TPC 0x01000000 +#define L2C_CFG_CPC 0x00800000 +#define L2C_CFG_FRAN 0x00200000 +#define L2C_CFG_SS_MASK 0x00180000 +#define L2C_CFG_SS_256 0x00000000 +#define L2C_CFG_CPIM 0x00040000 +#define L2C_CFG_TPIM 0x00020000 +#define L2C_CFG_LIM 0x00010000 +#define L2C_CFG_PMUX_MASK 0x00007000 +#define L2C_CFG_PMUX_SNP 0x00000000 +#define L2C_CFG_PMUX_IF 0x00001000 +#define L2C_CFG_PMUX_DF 0x00002000 +#define L2C_CFG_PMUX_DS 0x00003000 +#define L2C_CFG_PMIM 0x00000800 +#define L2C_CFG_TPEI 0x00000400 +#define L2C_CFG_CPEI 0x00000200 +#define L2C_CFG_NAM 0x00000100 +#define L2C_CFG_SMCM 0x00000080 +#define L2C_CFG_NBRM 0x00000040 +#define DCRN_L2C0_CMD 0x031 +#define L2C_CMD_CLR 0x80000000 +#define L2C_CMD_DIAG 0x40000000 +#define L2C_CMD_INV 0x20000000 +#define L2C_CMD_CCP 0x10000000 +#define L2C_CMD_CTE 0x08000000 +#define L2C_CMD_STRC 0x04000000 +#define L2C_CMD_STPC 0x02000000 +#define L2C_CMD_RPMC 0x01000000 +#define L2C_CMD_HCC 0x00800000 +#define DCRN_L2C0_ADDR 0x032 +#define DCRN_L2C0_DATA 0x033 +#define DCRN_L2C0_SR 0x034 +#define L2C_SR_CC 0x80000000 +#define L2C_SR_CPE 0x40000000 +#define L2C_SR_TPE 0x20000000 +#define L2C_SR_LRU 0x10000000 +#define L2C_SR_PCS 0x08000000 +#define DCRN_L2C0_REVID 0x035 +#define DCRN_L2C0_SNP0 0x036 +#define DCRN_L2C0_SNP1 0x037 +#define L2C_SNP_BA_MASK 0xffff0000 +#define L2C_SNP_SSR_MASK 0x0000f000 +#define L2C_SNP_SSR_32G 0x0000f000 +#define L2C_SNP_ESR 0x00000800 +#endif /* CONFIG_440GX */ + +/* + * PCI-X definitions + */ +#define PCIX0_REG_BASE 0x20ec80000ULL +#define PCIX0_REG_SIZE 0x200 + +#define PCIX0_VENDID 0x000 +#define PCIX0_DEVID 0x002 +#define PCIX0_COMMAND 0x004 +#define PCIX0_STATUS 0x006 +#define PCIX0_REVID 0x008 +#define PCIX0_CLS 0x009 +#define PCIX0_CACHELS 0x00c +#define PCIX0_LATTIM 0x00d +#define PCIX0_HDTYPE 0x00e +#define PCIX0_BIST 0x00f +#define PCIX0_BAR0L 0x010 +#define PCIX0_BAR0H 0x014 +#define PCIX0_BAR1 0x018 +#define PCIX0_BAR2L 0x01c +#define PCIX0_BAR2H 0x020 +#define PCIX0_BAR3 0x024 +#define PCIX0_CISPTR 0x028 +#define PCIX0_SBSYSVID 0x02c +#define PCIX0_SBSYSID 0x02e +#define PCIX0_EROMBA 0x030 +#define PCIX0_CAP 0x034 +#define PCIX0_RES0 0x035 +#define PCIX0_RES1 0x036 +#define PCIX0_RES2 0x038 +#define PCIX0_INTLN 0x03c +#define PCIX0_INTPN 0x03d +#define PCIX0_MINGNT 0x03e +#define PCIX0_MAXLTNCY 0x03f +#define PCIX0_BRDGOPT1 0x040 +#define PCIX0_BRDGOPT2 0x044 +#define PCIX0_ERREN 0x050 +#define PCIX0_ERRSTS 0x054 +#define PCIX0_PLBBESR 0x058 +#define PCIX0_PLBBEARL 0x05c +#define PCIX0_PLBBEARH 0x060 +#define PCIX0_POM0LAL 0x068 +#define PCIX0_POM0LAH 0x06c +#define PCIX0_POM0SA 0x070 +#define PCIX0_POM0PCIAL 0x074 +#define PCIX0_POM0PCIAH 0x078 +#define PCIX0_POM1LAL 0x07c +#define PCIX0_POM1LAH 0x080 +#define PCIX0_POM1SA 0x084 +#define PCIX0_POM1PCIAL 0x088 +#define PCIX0_POM1PCIAH 0x08c +#define PCIX0_POM2SA 0x090 +#define PCIX0_PIM0SAL 0x098 +#define PCIX0_PIM0SA PCIX0_PIM0SAL +#define PCIX0_PIM0LAL 0x09c +#define PCIX0_PIM0LAH 0x0a0 +#define PCIX0_PIM1SA 0x0a4 +#define PCIX0_PIM1LAL 0x0a8 +#define PCIX0_PIM1LAH 0x0ac +#define PCIX0_PIM2SAL 0x0b0 +#define PCIX0_PIM2SA PCIX0_PIM2SAL +#define PCIX0_PIM2LAL 0x0b4 +#define PCIX0_PIM2LAH 0x0b8 +#define PCIX0_OMCAPID 0x0c0 +#define PCIX0_OMNIPTR 0x0c1 +#define PCIX0_OMMC 0x0c2 +#define PCIX0_OMMA 0x0c4 +#define PCIX0_OMMUA 0x0c8 +#define PCIX0_OMMDATA 0x0cc +#define PCIX0_OMMEOI 0x0ce +#define PCIX0_PMCAPID 0x0d0 +#define PCIX0_PMNIPTR 0x0d1 +#define PCIX0_PMC 0x0d2 +#define PCIX0_PMCSR 0x0d4 +#define PCIX0_PMCSRBSE 0x0d6 +#define PCIX0_PMDATA 0x0d7 +#define PCIX0_PMSCRR 0x0d8 +#define PCIX0_CAPID 0x0dc +#define PCIX0_NIPTR 0x0dd +#define PCIX0_CMD 0x0de +#define PCIX0_STS 0x0e0 +#define PCIX0_IDR 0x0e4 +#define PCIX0_CID 0x0e8 +#define PCIX0_RID 0x0ec +#define PCIX0_PIM0SAH 0x0f8 +#define PCIX0_PIM2SAH 0x0fc +#define PCIX0_MSGIL 0x100 +#define PCIX0_MSGIH 0x104 +#define PCIX0_MSGOL 0x108 +#define PCIX0_MSGOH 0x10c +#define PCIX0_IM 0x1f8 + +#define IIC_OWN 0x55 +#define IIC_CLOCK 50 + +#undef NR_UICS +#define NR_UICS 2 +#define UIC_CASCADE_MASK 0x0003 /* bits 30 & 31 */ + +#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i] + +#include + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_IBM44x_H__ */ +#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/ibm4xx.h cset-v2.4.20/include/asm-ppc/ibm4xx.h --- cset-v2.4.20~/include/asm-ppc/ibm4xx.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/ibm4xx.h 2004-11-01 22:39:04.000000000 +0900 @@ -0,0 +1,114 @@ +/* + * + * Copyright (c) 1999 Grant Erickson + * + * Module name: ibm4xx.h + * + * Description: + * A generic include file which pulls in appropriate include files + * for specific board types based on configuration settings. + * + */ + +#ifdef __KERNEL__ +#ifndef __ASM_IBM4XX_H__ +#define __ASM_IBM4XX_H__ + +#include +#include + +#ifdef CONFIG_4xx + +#ifndef __ASSEMBLY__ +/* + * The "residual" board information structure the boot loader passes + * into the kernel. + */ +extern unsigned char __res[]; + +/* Device Control Registers */ + +#define stringify(s) tostring(s) +#define tostring(s) #s + +#define mfdcr_or_dflt(rn,default_rval) \ + ({unsigned int rval; \ + if (rn == 0) \ + rval = default_rval; \ + else \ + asm volatile("mfdcr %0," stringify(rn) : "=r" (rval)); \ + rval;}) + +/* R/W of indirect DCRs make use of standard naming conventions for DCRs */ + +#define mfdcri(base, reg) \ +({ \ + mtdcr(base##_CFGADDR, base##_##reg); \ + mfdcr(base##_CFGDATA); \ +}) + +#define mtdcri(base, reg, data) \ +do { \ + mtdcr(base##_CFGADDR, base##_##reg); \ + mtdcr(base##_CFGDATA, data); \ +} while (0) +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_4xx */ + +#ifdef CONFIG_40x + +#if defined(CONFIG_OAK) +#include +#endif + +#if defined(CONFIG_WALNUT) +#include +#endif + +#ifndef PPC4xx_MACHINE_NAME +#define PPC4xx_MACHINE_NAME "Unidentified 4xx class" +#endif + +/* IO_BASE is for PCI I/O. + * ISA not supported, just here to resolve copilation. + */ + +#ifndef _IO_BASE +#define _IO_BASE 0xe8000000 /* The PCI address window */ +#define _ISA_MEM_BASE 0 +#define PCI_DRAM_OFFSET 0 +#endif + +#elif CONFIG_44x + +#if defined(CONFIG_EBONY) +#include +#endif + +#if defined(CONFIG_OCOTEA) +#include +#endif + +#endif /* CONFIG_40x */ + +#ifndef __ASSEMBLY__ +#if defined(EMAC_NUMS) && EMAC_NUMS > 0 +/* + * Per EMAC map of PHY ids which should be probed by emac_probe. + * Different EMACs can have overlapping maps. + * + * Note, this map uses inverse logic for bits: + * 0 - id should be probed + * 1 - id should be ignored + * + * Default value of 0x00000000 - will result in usual + * auto-detection logic. + * + */ +extern u32 emac_phy_map[EMAC_NUMS]; +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_IBM4XX_H__ */ +#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/io.h cset-v2.4.20/include/asm-ppc/io.h --- cset-v2.4.20~/include/asm-ppc/io.h 2004-10-25 15:01:57.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/io.h 2004-11-02 17:40:59.000000000 +0900 @@ -6,7 +6,9 @@ #define _PPC_IO_H #include +#include #include +#include #include #include @@ -24,8 +26,8 @@ #define PREP_ISA_MEM_BASE 0xc0000000 #define PREP_PCI_DRAM_OFFSET 0x80000000 -#if defined(CONFIG_4xx) -#include +#if defined(CONFIG_40x) +#include #elif defined(CONFIG_8xx) #include #elif defined(CONFIG_8260) @@ -186,14 +188,15 @@ * Map in an area of physical address space, for accessing * I/O devices etc. */ -extern void *__ioremap(unsigned long address, unsigned long size, +extern void *__ioremap(phys_addr_t address, unsigned long size, unsigned long flags); -extern void *ioremap(unsigned long address, unsigned long size); +extern void *ioremap(phys_addr_t address, unsigned long size); +extern void *ioremap64(unsigned long long address, unsigned long size); #define ioremap_nocache(addr, size) ioremap((addr), (size)) extern void iounmap(void *addr); extern unsigned long iopa(unsigned long addr); extern unsigned long mm_ptov(unsigned long addr) __attribute__ ((const)); -extern void io_block_mapping(unsigned long virt, unsigned long phys, +extern void io_block_mapping(unsigned long virt, phys_addr_t phys, unsigned int size, int flags); /* @@ -250,7 +253,7 @@ /* * Change "struct page" to physical address. */ -#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT) +#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + PPC_MEMSTART) #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) #endif /* __KERNEL__ */ @@ -367,11 +370,43 @@ return 0; } -/* Nothing to do */ +#ifdef CONFIG_NOT_COHERENT_CACHE + +/* + * DMA-consistent mapping functions for PowerPCs that don't support + * cache snooping. These allocate/free a region of uncached mapped + * memory space for use with DMA devices. Alternatively, you could + * allocate the space "normally" and use the cache management functions + * to ensure it is consistent. + */ +extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); +extern void consistent_free(void *vaddr); +extern void consistent_sync(void *vaddr, size_t size, int rw); +extern void consistent_sync_page(struct page *page, unsigned long offset, + size_t size, int rw); + +#define dma_cache_inv(_start,_size) \ + invalidate_dcache_range(_start, (_start + _size)) +#define dma_cache_wback(_start,_size) \ + clean_dcache_range(_start, (_start + _size)) +#define dma_cache_wback_inv(_start,_size) \ + flush_dcache_range(_start, (_start + _size)) + +#else /* ! CONFIG_NOT_COHERENT_CACHE */ + +/* + * Cache coherent cores. + */ #define dma_cache_inv(_start,_size) do { } while (0) #define dma_cache_wback(_start,_size) do { } while (0) #define dma_cache_wback_inv(_start,_size) do { } while (0) -#endif +#define consistent_alloc(gfp, size, handle) NULL +#define consistent_free(addr, size) do { } while (0) +#define consistent_sync(addr, size, rw) do { } while (0) +#define consistent_sync_page(pg, off, sz, rw) do { } while (0) + +#endif /* CONFIG_NOT_COHERENT_CACHE */ +#endif /* _PPC_IO_H */ #endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/irq.h cset-v2.4.20/include/asm-ppc/irq.h --- cset-v2.4.20~/include/asm-ppc/irq.h 2004-10-25 14:59:58.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/irq.h 2004-11-02 17:41:00.000000000 +0900 @@ -13,8 +13,35 @@ extern void disable_irq_nosync(unsigned int); extern void enable_irq(unsigned int); -#if defined(CONFIG_4xx) +/* + * These constants are used for passing information about interrupt + * signal polarity and level/edge sensing to the low-level PIC chip + * drivers. + */ +#define IRQ_SENSE_MASK 0x1 +#define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */ +#define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */ + +#define IRQ_POLARITY_MASK 0x2 +#define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */ +#define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */ + +#if defined(CONFIG_40x) +#include + +#ifndef NR_BOARD_IRQS +#define NR_BOARD_IRQS 0 +#endif + +#ifndef UIC_WIDTH /* Number of interrupts per device */ +#define UIC_WIDTH 32 +#endif + +#ifndef NR_UICS /* number of UIC devices */ +#define NR_UICS 1 +#endif +#if defined (CONFIG_403) /* * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has * 32 possible interrupts, a majority of which are not implemented on @@ -22,6 +49,14 @@ * there are eight internal interrupts for the on-chip serial port * (SPU), DMA controller, and JTAG controller. * + */ + +#define NR_AIC_IRQS 32 +#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS) + +#elif !defined (CONFIG_403) + +/* * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32 * possible interrupts as well. There are seven, configurable external * interrupt pins and there are 17 internal interrupts for the on-chip @@ -29,23 +64,21 @@ * */ -#define NR_IRQS 32 -#define AIC_INT0 (0) -#define AIC_INT4 (4) -#define AIC_INT5 (5) -#define AIC_INT6 (6) -#define AIC_INT7 (7) -#define AIC_INT8 (8) -#define AIC_INT9 (9) -#define AIC_INT10 (10) -#define AIC_INT11 (11) -#define AIC_INT27 (27) -#define AIC_INT28 (28) -#define AIC_INT29 (29) -#define AIC_INT30 (30) -#define AIC_INT31 (31) +#define NR_UIC_IRQS UIC_WIDTH +#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS) +#endif +static __inline__ int +irq_cannonicalize(int irq) +{ + return (irq); +} + +#elif defined(CONFIG_44x) +#include +#define NR_UIC_IRQS 32 +#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS) static __inline__ int irq_cannonicalize(int irq) @@ -123,7 +156,7 @@ return irq; } -#else /* CONFIG_4xx + CONFIG_8xx */ +#else /* CONFIG_40x + CONFIG_8xx */ /* * this is the # irq's for all ppc arch's (pmac/chrp/prep) * so it is the max of them all diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/mmu.h cset-v2.4.20/include/asm-ppc/mmu.h --- cset-v2.4.20~/include/asm-ppc/mmu.h 2004-10-25 15:06:20.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/mmu.h 2004-11-01 22:39:04.000000000 +0900 @@ -13,6 +13,18 @@ #ifndef __ASSEMBLY__ +/* + * Define physical address type. Machines using split size + * virtual/physical addressing like 32-bit virtual / 36-bit + * physical need a larger than native word size type. -Matt + */ +#ifdef CONFIG_PTE_64BIT +typedef unsigned long long phys_addr_t; +extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t); +#else +typedef unsigned long phys_addr_t; +#endif + /* Default "unsigned long" context */ typedef unsigned long mm_context_t; @@ -326,5 +338,54 @@ #define TLB_M 0x00000002 /* Memory is coherent */ #define TLB_G 0x00000001 /* Memory is guarded from prefetch */ +/* + * PPC44x support + */ +#define PPC44x_MMUCR_TID 0x000000ff +#define PPC44x_MMUCR_STS 0x00010000 + +#define PPC44x_TLB_PAGEID 0 +#define PPC44x_TLB_XLAT 1 +#define PPC44x_TLB_ATTRIB 2 + +/* Page identification fields */ +#define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */ +#define PPC44x_TLB_VALID 0x00000200 /* Valid flag */ +#define PPC44x_TLB_TS 0x00000100 /* Translation address space */ +#define PPC44x_TLB_PAGESZ_MASK 0x000000f0 +#define PPC44x_TLB_PAGESZ(x) (x << 4) +#define PPC44x_PAGESZ_1K 0 +#define PPC44x_PAGESZ_4K 1 +#define PPC44x_PAGESZ_16K 2 +#define PPC44x_PAGESZ_64K 3 +#define PPC44x_PAGESZ_256K 4 +#define PPC44x_PAGESZ_1M 5 +#define PPC44x_PAGESZ_16M 7 +#define PPC44x_PAGESZ_256M 9 + +/* Translation fields */ +#define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */ +#define PPC44x_TLB_ERPN_MASK 0x0000000f + +/* Storage attribute and access control fields */ +#define PPC44x_TLB_ATTR_MASK 0x0000ff80 +#define PPC44x_TLB_U0 0x00008000 /* User 0 */ +#define PPC44x_TLB_U1 0x00004000 /* User 1 */ +#define PPC44x_TLB_U2 0x00002000 /* User 2 */ +#define PPC44x_TLB_U3 0x00001000 /* User 3 */ +#define PPC44x_TLB_W 0x00000800 /* Caching is write-through */ +#define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */ +#define PPC44x_TLB_M 0x00000200 /* Memory is coherent */ +#define PPC44x_TLB_G 0x00000100 /* Memory is guarded */ +#define PPC44x_TLB_E 0x00000080 /* Memory is guarded */ + +#define PPC44x_TLB_PERM_MASK 0x0000003f +#define PPC44x_TLB_UX 0x00000020 /* User execution */ +#define PPC44x_TLB_UW 0x00000010 /* User write */ +#define PPC44x_TLB_UR 0x00000008 /* User read */ +#define PPC44x_TLB_SX 0x00000004 /* Super execution */ +#define PPC44x_TLB_SW 0x00000002 /* Super write */ +#define PPC44x_TLB_SR 0x00000001 /* Super read */ + #endif /* _PPC_MMU_H_ */ #endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/ocp.h cset-v2.4.20/include/asm-ppc/ocp.h --- cset-v2.4.20~/include/asm-ppc/ocp.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/ocp.h 2004-11-02 17:41:19.000000000 +0900 @@ -0,0 +1,191 @@ +/* + * ocp.h + * + * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org) + * Mipsys - France + * + " Derived from work (c) Armin Kuster akuster@pacbell.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * TODO: - Add get/put interface & fixup locking to provide same API for + * 2.4 and 2.5 + * - Rework PM callbacks + */ + +#ifdef __KERNEL__ +#ifndef __OCP_H__ +#define __OCP_H__ + +#include +#include +#include + +#include +#include +#include +#include + +#if defined(CONFIG_IBM_OCP) +#include +#endif + +#define OCP_MAX_IRQS 7 +#define MAX_EMACS 4 +#define OCP_IRQ_NA -1 /* used when ocp device does not have an irq */ +#define OCP_IRQ_MUL -2 /* used for ocp devices with multiply irqs */ +#define OCP_NULL_TYPE -1 /* used to mark end of list */ +#define OCP_CPM_NA 0 /* No Clock or Power Management avaliable */ +#define OCP_PADDR_NA 0 /* No MMIO registers */ + +#define OCP_ANY_ID (~0) +#define OCP_ANY_INDEX -1 + +extern struct list_head ocp_devices; +extern struct list_head ocp_drivers; +extern struct rw_semaphore ocp_devices_sem; +extern struct semaphore ocp_drivers_sem; + +struct ocp_device_id { + unsigned int vendor, function; /* Vendor and function ID or OCP_ANY_ID */ + unsigned long driver_data; /* Data private to the driver */ +}; + + +/* + * Static definition of an OCP device. + * + * @vendor: Vendor code. It is _STRONGLY_ discouraged to use + * the vendor code as a way to match a unique device, + * though I kept that possibility open, you should + * really define different function codes for different + * device types + * @function: This is the function code for this device. + * @index: This index is used for mapping the Nth function of a + * given core. This is typically used for cross-driver + * matching, like looking for a given MAL or ZMII from + * an EMAC or for getting to the proper set of DCRs. + * Indices are no longer magically calculated based on + * structure ordering, they have to be actually coded + * into the ocp_def to avoid any possible confusion + * I _STRONGLY_ (again ? wow !) encourage anybody relying + * on index mapping to encode the "target" index in an + * associated structure pointed to by "additions", see + * how it's done for the EMAC driver. + * @paddr: Device physical address (may not mean anything...) + * @irq: Interrupt line for this device (TODO: think about making + * an array with this) + * @pm: Currently, contains the bitmask in CPMFR DCR for the device + * @additions: Optionally points to a function specific structure + * providing additional informations for a given device + * instance. It's currently used by the EMAC driver for MAL + * channel & ZMII port mapping among others. + */ +struct ocp_def { + unsigned int vendor; + unsigned int function; + int index; + phys_addr_t paddr; + int irq; + unsigned long pm; + void *additions; +}; + + +/* Struct for a given device instance */ +struct ocp_device { + struct list_head link; + char name[80]; /* device name */ + const struct ocp_def *def; /* device definition */ + void *drvdata; /* driver data for this device */ + struct ocp_driver *driver; + u32 current_state; /* Current operating state. In ACPI-speak, + this is D0-D3, D0 being fully functional, + and D3 being off. */ +}; + +/* Structure for a device driver */ +struct ocp_driver { + const char *name; + const struct ocp_device_id *id_table; /* NULL if wants all devices */ + + int (*probe) (struct ocp_device *dev); /* New device inserted */ + void (*remove) (struct ocp_device *dev); /* Device removed (NULL if not a + hot-plug capable driver) */ + int (*save_state) (struct ocp_device *dev, u32 state); /* Save Device Context */ + int (*suspend) (struct ocp_device *dev, u32 state); /* Device suspended */ + int (*resume) (struct ocp_device *dev); /* Device woken up */ + int (*enable_wake) (struct ocp_device *dev, u32 state, int enable); + /* Enable wake event */ + struct list_head link; +}; + +/* Similar to the helpers above, these manipulate per-ocp_dev + * driver-specific data. Currently stored as ocp_dev::ocpdev, + * a void pointer, but it is not present on older kernels. + */ +static inline void * +ocp_get_drvdata(struct ocp_device *pdev) +{ + return pdev->drvdata; +} + +static inline void +ocp_set_drvdata(struct ocp_device *pdev, void *data) +{ + pdev->drvdata = data; +} + +#if defined (CONFIG_PM) +/* + * This is right for the IBM 405 and 440 but will need to be + * generalized if the OCP stuff gets used on other processors. + */ +static inline void +ocp_force_power_off(struct ocp_device *odev) +{ + mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm); +} + +static inline void +ocp_force_power_on(struct ocp_device *odev) +{ + mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm); +} +#else +#define ocp_force_power_off(x) (void)(x) +#define ocp_force_power_on(x) (void)(x) +#endif + +/* Register/Unregister an OCP driver */ +extern int ocp_register_driver(struct ocp_driver *drv); +extern void ocp_unregister_driver(struct ocp_driver *drv); + +/* Initialize the OCP management layer */ +extern int ocp_init(void); + +/* Find a device by index */ +extern struct ocp_device *ocp_find_device(unsigned int vendor, unsigned int function, int index); + + +#endif /* __OCP_H__ */ +#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/ocp_ids.h cset-v2.4.20/include/asm-ppc/ocp_ids.h --- cset-v2.4.20~/include/asm-ppc/ocp_ids.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/ocp_ids.h 2004-11-01 22:35:10.000000000 +0900 @@ -0,0 +1,127 @@ +/* + * FILE NAME: ocp_ids.h + * + * BRIEF MODULE DESCRIPTION: + * OCP device ids based on the ideas from PCI + * + * Maintained by: Armin + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Version 1.0 08/22/02 -Armin + * initial release + */ + +/* + * Vender device + * [xxxx] [xxxx] + * + * Keep in order, please + */ + +/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */ + +#define OCP_VENDOR_INVALID 0x0000 +#define OCP_VENDOR_ARM 0x0004 +#define OCP_VENDOR_IBM 0x1014 +#define OCP_VENDOR_MOTOROLA 0x1057 +#define OCP_VENDOR_XILINX 0x10ee +#define OCP_VENDOR_UNKNOWN 0xFFFF + +/* device identification */ + +/* define type */ +#define OCP_FUNC_INVALID 0x0000 + +/* system 0x0001 - 0x001F */ +#define OCP_FUNC_UIC 0x0001 + +/* Timers 0x0020 - 0x002F */ +#define OCP_FUNC_GPT 0x0020 /* General purpose timers */ +#define OCP_FUNC_RTC 0x0021 + +/* Serial 0x0030 - 0x006F*/ +#define OCP_FUNC_16550 0x0031 +#define OCP_FUNC_SSP 0x0032 /* sync serial port */ +#define OCP_FUNC_SCP 0x0033 /* serial controller port */ +#define OCP_FUNC_SCC 0x0034 /* serial contoller */ +#define OCP_FUNC_SCI 0x0035 /* Smart card */ +#define OCP_FUNC_IIC 0x0040 +#define OCP_FUNC_USB 0x0050 +#define OCP_FUNC_IR 0x0060 + +/* Memory devices 0x0090 - 0x009F */ +#define OCP_FUNC_SDRAM 0x0091 +#define OCP_FUNC_DMA 0x0092 +#define OCP_FUNC_MAL 0x0093 + + /* Additional data */ + struct ocp_func_mal_data { + int num_tx_chans; /* Number of TX channels */ + int num_rx_chans; /* Number of RX channels */ + }; + +/* Display 0x00A0 - 0x00AF */ +#define OCP_FUNC_VIDEO 0x00A0 +#define OCP_FUNC_LED 0x00A1 +#define OCP_FUNC_LCD 0x00A2 + +/* Sound 0x00B0 - 0x00BF */ +#define OCP_FUNC_AUDIO 0x00B0 + +/* Mass Storage 0x00C0 - 0xxCF */ +#define OCP_FUNC_IDE 0x00C0 + +/* Misc 0x00D0 - 0x00DF*/ +#define OCP_FUNC_GPIO 0x00D0 +#define OCP_FUNC_ZMII 0x00D1 + +/* Network 0x0200 - 0x02FF */ +#define OCP_FUNC_EMAC 0x0200 + + /* Additional data + * + * Note about mdio_idx: When you have a zmii, it's usually + * not necessary, it covers the case of the 405EP which has + * the MDIO lines on EMAC0 only + */ + struct ocp_func_emac_data { + int zmii_idx; /* ZMII device index or -1 */ + int zmii_mux; /* ZMII input of this EMAC */ + int mal_idx; /* MAL device index */ + int mal_rx_chan; /* MAL rx channel number */ + int mal_tx1_chan; /* MAL tx channel 1 number */ + int mal_tx2_chan; /* MAL tx channel 2 number */ + int wol_irq; /* WOL interrupt */ + int mdio_idx; /* EMAC idx of MDIO master or -1 */ + }; + +/* Bridge devices 0xE00 - 0xEFF */ +#define OCP_FUNC_HOST 0x0E00 +#define OCP_FUNC_DCR 0x0E01 +#define OCP_FUNC_OPB 0x0E02 +#define OCP_FUNC_PHY 0x0E03 +#define OCP_FUNC_EXT 0x0E04 +#define OCP_FUNC_PCI 0x0E05 +#define OCP_FUNC_PLB 0x0E06 + +#define OCP_FUNC_UNKNOWN 0xFFFF diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/page.h cset-v2.4.20/include/asm-ppc/page.h --- cset-v2.4.20~/include/asm-ppc/page.h 2004-10-25 15:01:51.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/page.h 2004-11-02 17:40:59.000000000 +0900 @@ -7,7 +7,11 @@ /* PAGE_SHIFT determines the page size */ #define PAGE_SHIFT 12 #define PAGE_SIZE (1UL << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) +/* + * Subtle: this is an int (not an unsigned long) and so it + * gets extended to 64 bits the way want (i.e. with 1s). -- paulus + */ +#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) #ifdef __KERNEL__ #include @@ -17,6 +21,20 @@ #define KERNELBASE PAGE_OFFSET #ifndef __ASSEMBLY__ +/* + * The basic type of a PTE - 64 bits for those CPUs with > 32 bit + * physical addressing. For now this just the IBM PPC440. + */ +#ifdef CONFIG_PTE_64BIT +typedef unsigned long long pte_basic_t; +#define PTE_SHIFT (PAGE_SHIFT - 3) /* 512 ptes per page */ +#define PTE_FMT "%16Lx" +#else +typedef unsigned long pte_basic_t; +#define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */ +#define PTE_FMT "%.8lx" +#endif + #include /* for xmon definition */ #ifdef CONFIG_XMON @@ -38,7 +56,7 @@ /* * These are used to make use of C type-checking.. */ -typedef struct { unsigned long pte; } pte_t; +typedef struct { pte_basic_t pte; } pte_t; typedef struct { unsigned long pmd; } pmd_t; typedef struct { unsigned long pgd; } pgd_t; typedef struct { unsigned long pgprot; } pgprot_t; @@ -86,6 +104,17 @@ extern void clear_user_page(void *page, unsigned long vaddr); extern void copy_user_page(void *to, void *from, unsigned long vaddr); +extern unsigned long ppc_memstart; +extern unsigned long ppc_memoffset; +#ifndef CONFIG_APUS +#define PPC_MEMSTART 0 +#define PPC_MEMOFFSET PAGE_OFFSET +#else +#define PPC_MEMSTART ppc_memstart +#define PPC_MEMOFFSET ppc_memoffset +#endif + +#if defined(CONFIG_APUS) && !defined(MODULE) /* map phys->virtual and virtual->phys for RAM pages */ static inline unsigned long ___pa(unsigned long v) { @@ -113,8 +142,13 @@ return (void*) v; } +#else +#define ___pa(vaddr) ((vaddr)-PPC_MEMOFFSET) +#define ___va(paddr) ((paddr)+PPC_MEMOFFSET) +#endif + #define __pa(x) ___pa ((unsigned long)(x)) -#define __va(x) ___va ((unsigned long)(x)) +#define __va(x) ((void *)(___va((unsigned long)(x)))) #define MAP_PAGE_RESERVED (1<<15) #define virt_to_page(kaddr) (mem_map + (((unsigned long)kaddr-PAGE_OFFSET) >> PAGE_SHIFT)) diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/pc_serial.h cset-v2.4.20/include/asm-ppc/pc_serial.h --- cset-v2.4.20~/include/asm-ppc/pc_serial.h 1970-01-01 09:00:00.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/pc_serial.h 2004-11-01 22:35:10.000000000 +0900 @@ -0,0 +1,129 @@ +/* + * BK Id: %F% %I% %G% %U% %#% + * + * include/asm-ppc/pc_serial.h + * + * This is basically a copy of include/asm-i386/serial.h. + * It is used on platforms which have an ISA bus and thus are likely + * to have PC-style serial ports at the legacy I/O port addresses. + * It also includes the definitions for the fourport, accent, boca + * and hub6 multiport serial cards, although I have never heard of + * anyone using any of those on a PPC platform. -- paulus + */ + +#include + +/* + * This assumes you have a 1.8432 MHz clock for your UART. + * + * It'd be nice if someone built a serial card with a 24.576 MHz + * clock, since the 16550A is capable of handling a top speed of 1.5 + * megabits/second; but this requires the faster clock. + */ +#define BASE_BAUD ( 1843200 / 16 ) + +#ifdef CONFIG_SERIAL_MANY_PORTS +#define RS_TABLE_SIZE 64 +#else +#define RS_TABLE_SIZE 4 +#endif + +/* Standard COM flags (except for COM4, because of the 8514 problem) */ +#ifdef CONFIG_SERIAL_DETECT_IRQ +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) +#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) +#else +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) +#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF +#endif + +#ifdef CONFIG_SERIAL_MANY_PORTS +#define FOURPORT_FLAGS ASYNC_FOURPORT +#define ACCENT_FLAGS 0 +#define BOCA_FLAGS 0 +#define HUB6_FLAGS 0 +#endif + +/* + * The following define the access methods for the HUB6 card. All + * access is through two ports for all 24 possible chips. The card is + * selected through the high 2 bits, the port on that card with the + * "middle" 3 bits, and the register on that port with the bottom + * 3 bits. + * + * While the access port and interrupt is configurable, the default + * port locations are 0x302 for the port control register, and 0x303 + * for the data read/write register. Normally, the interrupt is at irq3 + * but can be anything from 3 to 7 inclusive. Note that using 3 will + * require disabling com2. + */ + +#define C_P(card,port) (((card)<<6|(port)<<3) + 1) + +#define STD_SERIAL_PORT_DEFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ + { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ + { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ + { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ + + +#ifdef CONFIG_SERIAL_MANY_PORTS +#define EXTRA_SERIAL_PORT_DEFNS \ + { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \ + { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \ + { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \ + { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \ + { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \ + { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \ + { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \ + { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \ + { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \ + { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \ + { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \ + { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \ + { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \ + { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \ + { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \ + { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \ + { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \ + { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \ + { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \ + { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \ + { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \ + { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \ + { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \ + { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \ + { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \ + { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \ + { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \ + { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */ +#else +#define EXTRA_SERIAL_PORT_DEFNS +#endif + +/* You can have up to four HUB6's in the system, but I've only + * included two cards here for a total of twelve ports. + */ +#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS)) +#define HUB6_SERIAL_PORT_DFNS \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */ +#else +#define HUB6_SERIAL_PORT_DFNS +#endif + +#define SERIAL_PORT_DFNS \ + STD_SERIAL_PORT_DEFNS \ + EXTRA_SERIAL_PORT_DEFNS \ + HUB6_SERIAL_PORT_DFNS diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/pci-bridge.h cset-v2.4.20/include/asm-ppc/pci-bridge.h --- cset-v2.4.20~/include/asm-ppc/pci-bridge.h 2004-10-25 14:59:43.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/pci-bridge.h 2004-11-02 17:44:04.000000000 +0900 @@ -69,6 +69,11 @@ struct pci_ops *ops; volatile unsigned int *cfg_addr; volatile unsigned char *cfg_data; + /* + * If set, indirect method will set the cfg_type bit as + * needed to generate type 1 configuration transactions. + */ + int set_cfg_type; /* Currently, we limit ourselves to 1 IO range and 3 mem * ranges since the common pci_bus structure can't handle more diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/pci.h cset-v2.4.20/include/asm-ppc/pci.h --- cset-v2.4.20~/include/asm-ppc/pci.h 2004-10-25 15:05:41.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/pci.h 2004-11-02 17:40:59.000000000 +0900 @@ -5,6 +5,14 @@ #define __PPC_PCI_H #ifdef __KERNEL__ +#include +#include +#include +#include +#include + +struct pci_dev; + /* Values for the `which' argument to sys_pciconfig_iobase syscall. */ #define IOBASE_BRIDGE_NUMBER 0 #define IOBASE_MEMORY 1 @@ -46,18 +54,12 @@ extern unsigned long pci_phys_to_bus(unsigned long pa, int busnr); extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr); -/* Dynamic DMA Mapping stuff, stolen from i386 - * ++ajoshi + /* + * Dynamic DMA Mapping stuff + * Originally stolen from i386 by ajoshi and updated by paulus + * Non-consistent cache support by Dan Malek */ -#include -#include -#include -#include -#include - -struct pci_dev; - /* The PCI address space does equal the physical memory * address space. The networking and block device layers use * this boolean for bounce buffer decisions. @@ -94,8 +96,8 @@ static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction) { - if (direction == PCI_DMA_NONE) - BUG(); + BUG_ON(direction == PCI_DMA_NONE); + consistent_sync(ptr, size, direction); return virt_to_bus(ptr); } @@ -120,10 +122,11 @@ * to pci_map_single, but takes a struct page instead of a virtual address */ static inline dma_addr_t pci_map_page(struct pci_dev *hwdev, struct page *page, - unsigned long offset, size_t size, int direction) + unsigned long offset, size_t size, + int direction) { - if (direction == PCI_DMA_NONE) - BUG(); + BUG_ON(direction == PCI_DMA_NONE); + consistent_sync_page(page, offset, size, direction); return (page - mem_map) * PAGE_SIZE + PCI_DRAM_OFFSET + offset; } @@ -139,7 +142,8 @@ * mode for DMA. This is the scather-gather version of the * above pci_map_single interface. Here the scatter gather list * elements are each tagged with the appropriate dma address - * and length. They are obtained via sg_dma_{address,length}(SG). + * and length. They are obtained via sg_dma_{address,len}(SG), + * defined in . * * NOTE: An implementation may be able to use a smaller number of * DMA address/length pairs than there are SG table elements. @@ -167,11 +171,16 @@ else if (!sg[i].address && !sg[i].page) BUG(); - if (sg[i].address) + if (sg[i].address) { + consistent_sync(sg[i].address, sg[i].length, direction); sg[i].dma_address = virt_to_bus(sg[i].address); - else + } else { + consistent_sync_page(sg[i].page, sg[i].offset, + sg[i].length, direction); sg[i].dma_address = page_to_bus(sg[i].page) + sg[i].offset; } + sg[i].dma_length = sg[i].length; + } return nents; } @@ -183,8 +192,7 @@ static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction) { - if (direction == PCI_DMA_NONE) - BUG(); + BUG_ON(direction == PCI_DMA_NONE); /* nothing to do */ } @@ -201,9 +209,9 @@ dma_addr_t dma_handle, size_t size, int direction) { - if (direction == PCI_DMA_NONE) - BUG(); - /* nothing to do */ + BUG_ON(direction == PCI_DMA_NONE); + + consistent_sync(bus_to_virt(dma_handle), size, direction); } /* Make physical memory consistent for a set of streaming @@ -216,9 +224,17 @@ struct scatterlist *sg, int nelems, int direction) { - if (direction == PCI_DMA_NONE) - BUG(); - /* nothing to do */ + int i; + + BUG_ON(direction == PCI_DMA_NONE); + + for (i = 0; i < nelems; i++, sg++) { + if (sg->address) + consistent_sync(sg->address, sg->length, direction); + else + consistent_sync_page(sg->page, sg->offset, + sg->length, direction); + } } /* Return whether the given PCI device DMA address mask can @@ -261,14 +277,6 @@ /* Nothing to do. */ } -/* These macros should be used after a pci_map_sg call has been done - * to get bus addresses of each of the SG entries and their lengths. - * You should only work with the number of sg entries pci_map_sg - * returns. - */ -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->length) - /* Return the index of the PCI controller for device PDEV. */ extern int pci_controller_num(struct pci_dev *pdev); diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/pgalloc.h cset-v2.4.20/include/asm-ppc/pgalloc.h --- cset-v2.4.20~/include/asm-ppc/pgalloc.h 2004-10-25 14:58:30.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/pgalloc.h 2004-11-02 17:40:59.000000000 +0900 @@ -9,6 +9,13 @@ #include #include +#ifdef CONFIG_PTE_64BIT +/* 44x uses an 8kB pgdir because it has 8-byte Linux PTEs. */ +#define PGDIR_ORDER 1 +#else +#define PGDIR_ORDER 0 +#endif + /* * This is handled very differently on the PPC since out page tables * are all 0's and I want to be able to use these zero'd pages elsewhere @@ -59,7 +66,7 @@ { pgd_t *ret; - if ((ret = (pgd_t *)__get_free_page(GFP_KERNEL)) != NULL) + if ((ret = (pgd_t *)__get_free_pages(GFP_KERNEL, PGDIR_ORDER)) != NULL) clear_page(ret); return ret; } diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/pgtable.h cset-v2.4.20/include/asm-ppc/pgtable.h --- cset-v2.4.20~/include/asm-ppc/pgtable.h 2004-10-25 15:01:06.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/pgtable.h 2004-11-02 17:40:59.000000000 +0900 @@ -14,16 +14,34 @@ #include #include -#if defined(CONFIG_4xx) -extern void local_flush_tlb_all(void); -extern void local_flush_tlb_mm(struct mm_struct *mm); -extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr); -extern void local_flush_tlb_range(struct mm_struct *mm, unsigned long start, - unsigned long end); +extern void _tlbie(unsigned long address); +extern void _tlbia(void); + +#ifdef CONFIG_4xx +#ifdef CONFIG_PIN_TLB +/* When pinning entries on the 4xx, we have to use a software function + * to ensure we don't remove them since there isn't any hardware support + * for this. + */ +#define __tlbia() _tlbia() +#else +#define __tlbia() asm volatile ("tlbia; sync" : : : "memory") +#endif + +static inline void local_flush_tlb_all(void) + { __tlbia(); } +static inline void local_flush_tlb_mm(struct mm_struct *mm) + { __tlbia(); } +static inline void local_flush_tlb_page(struct vm_area_struct *vma, + unsigned long vmaddr) + { _tlbie(vmaddr); } +static inline void local_flush_tlb_range(struct mm_struct *mm, + unsigned long start, unsigned long end) + { __tlbia(); } #define update_mmu_cache(vma, addr, pte) do { } while (0) #elif defined(CONFIG_8xx) -#define __tlbia() asm volatile ("tlbia" : : ) +#define __tlbia() asm volatile ("tlbia; sync" : : : "memory") static inline void local_flush_tlb_all(void) { __tlbia(); } @@ -31,7 +49,7 @@ { __tlbia(); } static inline void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr) - { __tlbia(); } + { _tlbie(vmaddr); } static inline void local_flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long end) { __tlbia(); } @@ -94,6 +112,13 @@ extern unsigned long va_to_phys(unsigned long address); extern pte_t *va_to_pte(unsigned long address); extern unsigned long ioremap_bot, ioremap_base; +extern unsigned long vmalloc_start; + +/* Start and end of the vmalloc area. */ +#define VMALLOC_START vmalloc_start +#define VMALLOC_END ioremap_bot +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) + #endif /* __ASSEMBLY__ */ /* @@ -139,13 +164,23 @@ * and ITLB, respectively (see "mmu.h" for definitions). */ -/* PMD_SHIFT determines the size of the area mapped by the second-level page tables */ -#define PMD_SHIFT 22 +/* + * The normal case is that PTEs are 32-bits and we have a 1-page + * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus + * + * For any >32-bit physical address platform, we can use the following + * two level page table layout where the pgdir is 8KB and the MS 13 bits + * are an index to the second level table. The combined pgdir/pmd first + * level has 2048 entries and the second level has 512 64-bit PTE entries. + * -Matt + */ +/* PMD_SHIFT determines the size of the area mapped by the PTE pages */ +#define PMD_SHIFT (PAGE_SHIFT + PTE_SHIFT) #define PMD_SIZE (1UL << PMD_SHIFT) #define PMD_MASK (~(PMD_SIZE-1)) -/* PGDIR_SHIFT determines what a third-level page table entry can map */ -#define PGDIR_SHIFT 22 +/* PGDIR_SHIFT determines what a top-level page table entry can map */ +#define PGDIR_SHIFT PMD_SHIFT #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) @@ -153,9 +188,10 @@ * entries per page directory level: our page-table tree is two-level, so * we don't really have any PMD directory. */ -#define PTRS_PER_PTE 1024 +#define PTRS_PER_PTE (1 << PTE_SHIFT) #define PTRS_PER_PMD 1 -#define PTRS_PER_PGD 1024 +#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT)) + #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) #define FIRST_USER_PGD_NR 0 @@ -163,51 +199,95 @@ #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS) #define pte_ERROR(e) \ - printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) + printk("%s:%d: bad pte "PTE_FMT".\n", __FILE__, __LINE__, pte_val(e)) #define pmd_ERROR(e) \ printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) #define pgd_ERROR(e) \ printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) /* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 64MB value just means that there will be a 64MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - * - * We no longer map larger than phys RAM with the BATs so we don't have - * to worry about the VMALLOC_OFFSET causing problems. We do have to worry - * about clashes between our early calls to ioremap() that start growing down - * from ioremap_base being run into the VM area allocations (growing upwards - * from VMALLOC_START). For this reason we have ioremap_bot to check when - * we actually run into our mappings setup in the early boot with the VM - * system. This really does become a problem for machines with good amounts - * of RAM. -- Cort - */ -#define VMALLOC_OFFSET (0x1000000) /* 16M */ -#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) -#define VMALLOC_END ioremap_bot - -/* * Bits in a linux-style PTE. These match the bits in the * (hardware-defined) PowerPC PTE as closely as possible. */ -#if defined(CONFIG_4xx) +#if defined(CONFIG_40x) + +/* There are several potential gotchas here. The 40x hardware TLBLO + field looks like this: + + 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 + RPN..................... 0 0 EX WR ZSEL....... W I M G + + Where possible we make the Linux PTE bits match up with this + + - bits 20 and 21 must be cleared, because we use 4k pages (4xx can + support down to 1k pages), this is done in the TLBMiss exception + handler. + - We use only zones 0 (for kernel pages) and 1 (for user pages) + of the 16 available. Bit 24-26 of the TLB are cleared in the TLB + miss handler. Bit 27 is PAGE_USER, thus selecting the correct + zone. + - PRESENT *must* be in the bottom two bits because swap cache + entries use the top 30 bits. Because 4xx doesn't support SMP + anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 + is cleared in the TLB miss handler before the TLB entry is loaded. + - All other bits of the PTE are loaded into TLBLO without + modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for + software PTE bits. We actually use use bits 21, 24, 25, and + 30 respectively for the software bits: ACCESSED, DIRTY, RW, and + PRESENT. +*/ + /* Definitions for 4xx embedded chips. */ #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */ -#define _PAGE_COHERENT 0x002 /* M: enforece memory coherence */ +#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */ #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */ #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */ #define _PAGE_USER 0x010 /* matches one of the zone permission bits */ -#define _PAGE_EXEC 0x020 /* software: i-cache coherency required */ -#define _PAGE_PRESENT 0x040 /* software: PTE contains a translation */ -#define _PAGE_DIRTY 0x100 /* C: page changed */ -#define _PAGE_RW 0x200 /* Writes permitted */ -#define _PAGE_ACCESSED 0x400 /* R: page referenced */ +#define _PAGE_RW 0x040 /* software: Writes permitted */ +#define _PAGE_DIRTY 0x080 /* software: dirty page */ +#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */ +#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */ +#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ +#define _PMD_PRESENT PAGE_MASK + +#elif defined(CONFIG_44x) +/* + * Definitions for PPC44x + * + * Because of the 3 word TLB entries to support 36-bit addressing, + * the attribute are difficult to map in such a fashion that they + * are easily loaded during exception processing. I decided to + * organize the entry so the ERPN is the only portion in the + * upper word of the PTE and the attribute bits below are packed + * in as sensibly as they can be in the area below a 4KB page size + * oriented RPN. This at least makes it easy to load the RPN and + * ERPN fields in the TLB. -Matt + * + * Note that these bits preclude future use of a page size + * less than 4KB. + */ +#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ +#define _PAGE_RW 0x00000002 /* S: Write permission */ +#define _PAGE_DIRTY 0x00000004 /* S: Page dirty */ +#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ +#define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */ +#define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */ +#define _PAGE_USER 0x00000040 /* S: User page */ +#define _PAGE_ENDIAN 0x00000080 /* H: E bit */ +#define _PAGE_GUARDED 0x00000100 /* H: G bit */ +#define _PAGE_COHERENT 0x00000200 /* H: M bit */ +#define _PAGE_FILE 0x00000400 /* S: nonlinear file mapping */ +#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ +#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ + +/* TODO: Add large page lowmem mapping support */ +#define _PMD_PRESENT 0 +#define _PMD_PRESENT_MASK (PAGE_MASK) +#define _PMD_BAD (~PAGE_MASK) + +/* ERPN in a PTE never gets cleared, ignore it */ +#define _PTE_NONE_MASK 0xffffffff00000000ULL #elif defined(CONFIG_8xx) /* Definitions for 8xx embedded chips. */ @@ -228,6 +308,16 @@ #define _PAGE_DIRTY 0x0200 /* software: page changed */ #define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */ +/* + * The 8xx TLB miss handler allegedly sets _PAGE_ACCESSED in the PTE + * for an address even if _PAGE_PRESENT is not set, as a performance + * optimization. This is a bug if you ever want to use swap unless + * _PAGE_ACCESSED is 2, which it isn't, or unless you have 8xx-specific + * definitions for __swp_entry etc. below, which would be gross. + * -- paulus + */ +#define _PTE_NONE_MASK _PAGE_ACCESSED + #else /* CONFIG_6xx */ /* Definitions for 60x, 740/750, etc. */ #define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ @@ -241,21 +331,19 @@ #define _PAGE_ACCESSED 0x100 /* R: page referenced */ #define _PAGE_EXEC 0x200 /* software: i-cache coherency required */ #define _PAGE_RW 0x400 /* software: user write access allowed */ + +#define _PTE_NONE_MASK _PAGE_HASHPTE + #endif -/* The non-standard PowerPC MMUs, which includes the 4xx and 8xx (and - * mabe 603e) have TLB miss handlers that unconditionally set the - * _PAGE_ACCESSED flag as a performance optimization. This causes - * problems for the page_none() macro, just like the HASHPTE flag does - * for the standard PowerPC MMUs. Depending upon the MMU configuration, - * either HASHPTE or ACCESSED will have to be masked to give us a - * proper pte_none() condition. +/* + * Some bits are only used on some cpu families... */ #ifndef _PAGE_HASHPTE #define _PAGE_HASHPTE 0 -#define _PTE_NONE_MASK _PAGE_ACCESSED -#else -#define _PTE_NONE_MASK _PAGE_HASHPTE +#endif +#ifndef _PTE_NONE_MASK +#define _PTE_NONE_MASK 0 #endif #ifndef _PAGE_SHARED #define _PAGE_SHARED 0 @@ -263,6 +351,12 @@ #ifndef _PAGE_HWWRITE #define _PAGE_HWWRITE 0 #endif +#ifndef _PAGE_HWEXEC +#define _PAGE_HWEXEC 0 +#endif +#ifndef _PAGE_EXEC +#define _PAGE_EXEC 0 +#endif #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) @@ -275,7 +369,16 @@ #define _PAGE_BASE _PAGE_PRESENT | _PAGE_ACCESSED #define _PAGE_WRENABLE _PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE -#define _PAGE_KERNEL _PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED +/* + * 44x wants _PAGE_GUARDED on all kernel pages for various reasons. + * Allegedly that doesn't hurt performance. -- paulus + */ +#ifdef CONFIG_44x +#define _PAGE_KERNEL _PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | _PAGE_HWEXEC | _PAGE_GUARDED +#else +#define _PAGE_KERNEL _PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | _PAGE_HWEXEC +#endif + #define _PAGE_IO _PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED #define PAGE_NONE __pgprot(_PAGE_BASE) @@ -333,7 +436,7 @@ #define pmd_present(pmd) ((pmd_val(pmd) & PAGE_MASK) != 0) #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0) -#define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> PAGE_SHIFT))) +#define pte_page(x) (mem_map+(unsigned long)((pte_val(x)-PPC_MEMSTART) >> PAGE_SHIFT)) #ifndef __ASSEMBLY__ /* @@ -389,7 +492,7 @@ * and a page entry and page directory to the page they refer to. */ -static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) +static inline pte_t mk_pte_phys(phys_addr_t physpage, pgprot_t pgprot) { pte_t pte; pte_val(pte) = physpage | pgprot_val(pgprot); @@ -399,7 +502,7 @@ #define mk_pte(page,pgprot) \ ({ \ pte_t pte; \ - pte_val(pte) = ((page - mem_map) << PAGE_SHIFT) | pgprot_val(pgprot); \ + pte_val(pte) = (((page - mem_map) << PAGE_SHIFT) + PPC_MEMSTART) | pgprot_val(pgprot); \ pte; \ }) @@ -414,6 +517,8 @@ * * pte_update clears and sets bit atomically, and returns * the old pte value. + * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant + * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits. */ static inline unsigned long pte_update(pte_t *p, unsigned long clr, unsigned long set) @@ -427,7 +532,7 @@ stwcx. %1,0,%3\n\ bne- 1b" : "=&r" (old), "=&r" (tmp), "=m" (*p) - : "r" (p), "r" (clr), "r" (set), "m" (*p) + : "r" ((unsigned long)(p+1) - 4), "r" (clr), "r" (set), "m" (*p) : "cc" ); return old; } @@ -494,7 +599,8 @@ return (pte_t *) pmd_page(*dir) + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)); } -extern pgd_t swapper_pg_dir[1024]; +extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; + extern void paging_init(void); /* diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/ppc4xx.h cset-v2.4.20/include/asm-ppc/ppc4xx.h --- cset-v2.4.20~/include/asm-ppc/ppc4xx.h 2004-10-25 15:04:46.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/ppc4xx.h 2004-11-01 22:35:11.000000000 +0900 @@ -1,285 +1,3 @@ /* * BK Id: SCCS/s.ppc4xx.h 1.3 05/17/01 18:14:25 cort */ -/* - * - * Copyright (c) 1999 Grant Erickson - * - * Module name: ppc4xx.h - * - * Description: - * A generic include file which pulls in appropriate include files - * for specific board types based on configuration settings. - * - */ - -#ifdef __KERNEL__ -#ifndef __PPC4XX_H__ -#define __PPC4XX_H__ - -#include - -#ifndef __ASSEMBLY__ - -#if defined(CONFIG_OAK) -#include -#endif - -#if defined(CONFIG_WALNUT) -#include -#endif - -/* IO_BASE is for PCI I/O. - * ISA not supported, just here to resolve copilation. - */ - -#ifndef _IO_BASE -#define _IO_BASE 0xe8000000 /* The PCI address window */ -#define _ISA_MEM_BASE 0 -#define PCI_DRAM_OFFSET 0 -#endif - -/* - * The "residual" board information structure the boot loader passes - * into the kernel. - */ -extern unsigned char __res[]; - -/* I don't know if this is general to 4xx, or unique to a specific - * processor or board. In any case it is easy to move. - */ -#define PPC4xx_PCI_IO_ADDR ((uint)0xe8000000) -#define PPC4xx_PCI_IO_SIZE ((uint)64*1024) -#define PPC4xx_PCI_CFG_ADDR ((uint)0xeec00000) -#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024) -#define PPC4xx_PCI_LCFG_ADDR ((uint)0xef400000) -#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024) -#define PPC4xx_ONB_IO_ADDR ((uint)0xef600000) -#define PPC4xx_ONB_IO_SIZE ((uint)4*1024) - -#endif /* __ASSEMBLY__ */ - -/* Device Control Registers unique to 4xx */ - -#define DCRN_BEAR 0x090 /* Bus Error Address Register */ -#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ -#define BESR_DMES 0x40000000 /* DMA Error Status */ -#define BESR_RWS 0x20000000 /* Read/Write Status */ -#define BESR_ETMASK 0x1C000000 /* Error Type */ -#define ET_PROT 0 -#define ET_PARITY 1 -#define ET_NCFG 2 -#define ET_BUSERR 4 -#define ET_BUSTO 6 -#define DCRN_CHCR0 0x0B1 /* Chip Control Register 1 */ -#define DCRN_CHCR1 0x0B2 /* Chip Control Register 2 */ -#define DCRN_CHPSR 0x0B4 /* Chip Pin Strapping */ -#define DCRN_CPMER 0x0B9 /* CPM Enable */ -#define DCRN_CPMFR 0x0BA /* CPM Force */ -#define CPM_IIC 0x80000000 /* IIC interface */ -#define CPM_PCI 0x40000000 /* PCI bridge */ -#define CPM_CPU 0x20000000 /* processor core */ -#define CPM_DMA 0x10000000 /* DMA controller */ -#define CPM_BRG 0x08000000 /* PLB to OPB bridge */ -#define CPM_DCP 0x04000000 /* CodePack */ -#define CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */ -#define CPM_SDRAM 0x01000000 /* SDRAM memory controller */ -#define CPM_PLB 0x00800000 /* PLB bus arbiter */ -#define CPM_GPIO 0x00400000 /* General Purpose IO (??) */ -#define CPM_UART0 0x00200000 /* serial port 0 */ -#define CPM_UART1 0x00100000 /* serial port 1 */ -#define CPM_UIC 0x00080000 /* Universal Interrupt Controller */ -#define CPM_TMRCLK 0x00040000 /* CPU timers */ -#define CPM_EMAC_MM 0x00020000 /* on-chip ethernet MM unit */ -#define CPM_EMAC_RM 0x00010000 /* on-chip ethernet RM unit */ -#define CPM_EMAC_TM 0x00008000 /* on-chip ethernet TM unit */ -#define DCRN_CPMSR 0x0B8 /* CPM Status */ - -#define DCRN_DMACR0 0x100 /* DMA Channel Control Register 0 */ -#define DCRN_DMACT0 0x101 /* DMA Count Register 0 */ -#define DCRN_DMADA0 0x102 /* DMA Destination Address Register 0 */ -#define DCRN_DMASA0 0x103 /* DMA Source Address Register 0 */ -#define DCRN_ASG0 0x104 /* DMA Scatter/Gather Descriptor Addr 0 */ - -#define DCRN_DMACR1 0x108 /* DMA Channel Control Register 1 */ -#define DCRN_DMACT1 0x109 /* DMA Count Register 1 */ -#define DCRN_DMADA1 0x10A /* DMA Destination Address Register 1 */ -#define DCRN_DMASA1 0x10B /* DMA Source Address Register 1 */ -#define DCRN_ASG1 0x10C /* DMA Scatter/Gather Descriptor Addr 1 */ - -#define DCRN_DMACR2 0x110 /* DMA Channel Control Register 2 */ -#define DCRN_DMACT2 0x111 /* DMA Count Register 2 */ -#define DCRN_DMADA2 0x112 /* DMA Destination Address Register 2 */ -#define DCRN_DMASA2 0x113 /* DMA Source Address Register 2 */ -#define DCRN_ASG2 0x114 /* DMA Scatter/Gather Descriptor Addr 2 */ - -#define DCRN_DMACR3 0x118 /* DMA Channel Control Register 3 */ -#define DCRN_DMACT3 0x119 /* DMA Count Register 3 */ -#define DCRN_DMADA3 0x11A /* DMA Destination Address Register 3 */ -#define DCRN_DMASA3 0x11B /* DMA Source Address Register 3 */ -#define DCRN_ASG3 0x11C /* DMA Scatter/Gather Descriptor Addr 3 */ - -#define DCRN_DMASR 0x120 /* DMA Status Register */ -#define DCRN_ASGC 0x123 /* DMA Scatter/Gather Command */ -#define DCRN_ADR 0x124 /* DMA Address Decode */ - -#define DCRN_SLP 0x125 /* DMA Sleep Register */ -#define DCRN_POL 0x126 /* DMA Polarity Register */ - - -#define DCRN_EBCCFGADR 0x012 /* Peripheral Controller Address */ -#define DCRN_EBCCFGDATA 0x013 /* Peripheral Controller Data */ -#define DCRN_EXISR 0x040 /* External Interrupt Status Register */ -#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ -#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ -#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ -#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ -#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ -#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ -#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ -#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ -#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ -#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ -#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ -#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ -#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ -#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ -#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ -#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ -#define IOCR_E0TE 0x80000000 -#define IOCR_E0LP 0x40000000 -#define IOCR_E1TE 0x20000000 -#define IOCR_E1LP 0x10000000 -#define IOCR_E2TE 0x08000000 -#define IOCR_E2LP 0x04000000 -#define IOCR_E3TE 0x02000000 -#define IOCR_E3LP 0x01000000 -#define IOCR_E4TE 0x00800000 -#define IOCR_E4LP 0x00400000 -#define IOCR_EDT 0x00080000 -#define IOCR_SOR 0x00040000 -#define IOCR_EDO 0x00008000 -#define IOCR_2XC 0x00004000 -#define IOCR_ATC 0x00002000 -#define IOCR_SPD 0x00001000 -#define IOCR_BEM 0x00000800 -#define IOCR_PTD 0x00000400 -#define IOCR_ARE 0x00000080 -#define IOCR_DRC 0x00000020 -#define IOCR_RDM(x) (((x) & 0x3) << 3) -#define IOCR_TCS 0x00000004 -#define IOCR_SCS 0x00000002 -#define IOCR_SPC 0x00000001 -#define DCRN_KIAR 0x014 /* Decompression Controller Address */ -#define DCRN_KIDR 0x015 /* Decompression Controller Data */ -#define DCRN_MALCR 0x180 /* MAL Configuration */ -#define MALCR_MMSR 0x80000000 /* MAL Software reset */ -#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ -#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ -#define MALCR_PLBP_3 0x00C00000 /* highest */ -#define MALCR_GA 0x00200000 /* Guarded Active Bit */ -#define MALCR_OA 0x00100000 /* Ordered Active Bit */ -#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ -#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ -#define MALCR_PLBLT_2 0x00020000 -#define MALCR_PLBLT_3 0x00010000 -#define MALCR_PLBLT_4 0x00008000 -#define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */ -#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ -#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ -#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ -#define MALCR_LEA 0x00000002 /* Locked Error Active */ -#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ -#define DCRN_MALDBR 0x183 /* Debug Register */ -#define DCRN_MALESR 0x181 /* Error Status */ -#define MALESR_EVB 0x80000000 /* Error Valid Bit */ -#define MALESR_CID 0x40000000 /* Channel ID Bit for channel 0 */ -#define MALESR_DE 0x00100000 /* Descriptor Error */ -#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ -#define MALESR_OTE 0x00040000 /* OPB Timeout Error */ -#define MALESR_OSE 0x00020000 /* OPB Slave Error */ -#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ -#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ -#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ -#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ -#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ -#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ -#define DCRN_MALIER 0x182 /* Interrupt Enable */ -#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ -#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ -#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ -#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ -#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ -#define DCRN_MALTXCARR 0x185 /* TX Channed Active Reset Register */ -#define DCRN_MALTXCASR 0x184 /* TX Channel Active Set Register */ -#define DCRN_MALTXDEIR 0x187 /* Tx Descriptor Error Interrupt */ -#define DCRN_MALTXEOBISR 0x186 /* Tx End of Buffer Interrupt Status */ -#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ -#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ -#define DCRN_MALRXCARR 0x191 /* RX Channed Active Reset Register */ -#define DCRN_MALRXCASR 0x190 /* RX Channel Active Set Register */ -#define DCRN_MALRXDEIR 0x193 /* Rx Descriptor Error Interrupt */ -#define DCRN_MALRXEOBISR 0x192 /* Rx End of Buffer Interrupt Status */ -#define DCRN_MALRXCTP0R 0x1C0 /* Channel Rx 0 Channel Table Pointer */ -#define DCRN_MALTXCTP0R 0x1A0 /* Channel Tx 0 Channel Table Pointer */ -#define DCRN_MALTXCTP1R 0x1A1 /* Channel Tx 1 Channel Table Pointer */ -#define DCRN_MALRCBS0 0x1E0 /* Channel Rx 0 Channel Buffer Size */ -#define DCRN_MEMCFGADR 0x010 /* Memory Controller Address */ -#define DCRN_MEMCFGDATA 0x011 /* Memory Controller Data */ -#define DCRN_OCMISARC 0x018 /* OCM Instr Side Addr Range Compare */ -#define DCRN_OCMISCR 0x019 /* OCM Instr Side Control */ -#define DCRN_OCMDSARC 0x01A /* OCM Data Side Addr Range Compare */ -#define DCRN_OCMDSCR 0x01B /* OCM Data Side Control */ -#define DCRN_PLB0_ACR 0x087 /* PLB Arbiter Control */ -#define DCRN_PLB0_BEAR 0x086 /* PLB Error Address */ -#define DCRN_PLB0_BESR 0x084 /* PLB Error Status */ -#define DCRN_PLLMR 0x0B0 /* PLL Mode */ -#define DCRN_POB0_BEAR 0x0A2 /* PLB to OPB Error Address */ -#define DCRN_POB0_BESR0 0x0A0 /* PLB to OPB Error Status Register 1 */ -#define DCRN_POB0_BESR1 0x0A4 /* PLB to OPB Error Status Register 1 */ -#define DCRN_UICCR 0x0C3 /* UIC Critical */ -#define DCRN_UICER 0x0C2 /* UIC Enable */ -#define DCRN_UICPR 0x0C4 /* UIC Polarity */ -#define DCRN_UICSR 0x0C0 /* UIC Status */ -#define DCRN_UICTR 0x0C5 /* UIC Triggering */ -#define DCRN_UICMSR 0x0C6 /* UIC Masked Status */ -#define DCRN_UICVR 0x0C7 /* UIC Vector */ -#define DCRN_UICVCR 0x0C8 /* UIC Vector Configuration */ -#define UIC_U0 0x80000000 /* UART0 */ -#define UIC_U1 0x40000000 /* UART1 */ -#define UIC_IIC 0x20000000 /* IIC */ -#define UIC_EM 0x10000000 /* External Master */ -#define UIC_PCI 0x08000000 /* PCI */ -#define UIC_D0 0x04000000 /* DMA Channel 0 */ -#define UIC_D1 0x02000000 /* DMA Channel 1 */ -#define UIC_D2 0x01000000 /* DMA Channel 2 */ -#define UIC_D3 0x00800000 /* DMA Channel 3 */ -#define UIC_EW 0x00400000 /* Ethernet Wake-up */ -#define UIC_MS 0x00200000 /* MAL SERR */ -#define UIC_MTE 0x00100000 /* MAL TX EOB */ -#define UIC_MRE 0x00080000 /* MAL RX EOB */ -#define UIC_MTD 0x00040000 /* MAL TX DE */ -#define UIC_MRD 0x00020000 /* MAL RX DE */ -#define UIC_E 0x00010000 /* Ethernet */ -#define UIC_EPS 0x00008000 /* External PCI SERR */ -#define UIC_EC 0x00004000 /* ECC Correctable Error */ -#define UIC_PPM 0x00002000 /* PCI Power Management */ -/* -** 0x00001000 reserved -** 0x00000800 reserved -** 0x00000400 reserved -** 0x00000200 reserved -** 0x00000100 reserved -** 0x00000080 reserved -*/ -#define UIC_EIR0 0x00000040 /* External IRQ 0 */ -#define UIC_EIR1 0x00000020 /* External IRQ 0 */ -#define UIC_EIR2 0x00000010 /* External IRQ 0 */ -#define UIC_EIR3 0x00000008 /* External IRQ 0 */ -#define UIC_EIR4 0x00000004 /* External IRQ 0 */ -#define UIC_EIR5 0x00000002 /* External IRQ 0 */ -#define UIC_EIR6 0x00000001 /* External IRQ 0 */ - -#endif /* __PPC4XX_H__ */ -#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/ppc4xx_pic.h cset-v2.4.20/include/asm-ppc/ppc4xx_pic.h --- cset-v2.4.20~/include/asm-ppc/ppc4xx_pic.h 2004-10-25 15:03:05.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/ppc4xx_pic.h 2004-11-02 17:44:06.000000000 +0900 @@ -15,11 +15,18 @@ #define __PPC4XX_PIC_H__ #include +#include /* External Global Variables */ - extern struct hw_interrupt_type *ppc4xx_pic; +/* + * The IBM4xxPIC_InitSenses table gives sense/polarity information + * for each interrupt, encoded using IRQ_SENSE_* and IRQ_POLARITY_* + * definitions from . -- paulus + */ +extern unsigned int ibm4xxPIC_NumInitSenses; +extern unsigned char *ibm4xxPIC_InitSenses; /* Function Prototypes */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/ppc4xx_serial.h cset-v2.4.20/include/asm-ppc/ppc4xx_serial.h --- cset-v2.4.20~/include/asm-ppc/ppc4xx_serial.h 2004-10-25 15:01:44.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/ppc4xx_serial.h 2004-11-01 22:35:11.000000000 +0900 @@ -1,104 +1,3 @@ /* * BK Id: SCCS/s.ppc4xx_serial.h 1.3 05/17/01 18:14:25 cort */ -/* - * Copyright 2000 MontaVista Software Inc. - * PPC405GP modifications - * Author: MontaVista Software, Inc. - * frank_rowand@mvista.com or source@mvista.com - * debbie_chu@mvista.com - * - * Module name: ppc405_serial.h - * - * Description: - * Macros, definitions, and data structures specific to the IBM PowerPC - * 405 on-chip serial port devices. - */ - -#ifdef __KERNEL__ -#ifndef __ASMPPC_PPC4xx_SERIAL_H -#define __ASMPPC_PPC4xx_SERIAL_H - -#include - -#ifdef CONFIG_SERIAL_MANY_PORTS -#define RS_TABLE_SIZE 64 -#else -#define RS_TABLE_SIZE 4 -#endif - -#define PPC405GP_UART0_INT 0 -#define PPC405GP_UART1_INT 1 - -/* -** 405GP UARTs are *not* PCI devices, so need to specify a non-pci memory -** address and an io_type of SERIAL_IO_MEM. -*/ - -#define PPC405GP_UART0_IO_BASE (u8 *) 0xef600300 -#define PPC405GP_UART1_IO_BASE (u8 *) 0xef600400 - -/* -** - there is no config option for this -** - this name could be more informative -** - also see arch/ppc/kernel/ppc405_serial.c -** -** #define CONFIG_PPC405GP_INTERNAL_CLOCK -*/ -#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK -#define BASE_BAUD 201600 -#else -#define BASE_BAUD 691200 -#endif - - -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF) -#endif - - -#ifdef CONFIG_STB03XXX - -#define UART0_IO_BASE 0x40040000 -#define UART0_INT 20 - -#define STD_SERIAL_PORT_DFNS \ - /* ttyS0 */ \ - { 0, BASE_BAUD, 0, UART0_INT, STD_COM_FLAGS, 0, 0, 0, 0, 0, 0, 0, \ - UART0_IO_BASE, 0, 0, 0, {}, {}, {}, SERIAL_IO_MEM, NULL }, - -#elif defined(CONFIG_UART1_DFLT_CONSOLE) - -#define STD_SERIAL_PORT_DFNS \ - /* ttyS1 */ \ - { 0, BASE_BAUD, 0, PPC405GP_UART1_INT, STD_COM_FLAGS, 0, 0, 0, 0, 0, 0, 0, \ - PPC405GP_UART1_IO_BASE, 0, 0, 0, {}, {}, {}, SERIAL_IO_MEM, NULL }, \ - /* ttyS0 */ \ - { 0, BASE_BAUD, 0, PPC405GP_UART0_INT, STD_COM_FLAGS, 0, 0, 0, 0, 0, 0, 0, \ - PPC405GP_UART0_IO_BASE, 0, 0, 0, {}, {}, {}, SERIAL_IO_MEM, NULL }, - -#else - -#define STD_SERIAL_PORT_DFNS \ - /* ttyS0 */ \ - { 0, BASE_BAUD, 0, PPC405GP_UART0_INT, STD_COM_FLAGS, 0, 0, 0, 0, 0, 0, 0, \ - PPC405GP_UART0_IO_BASE, 0, 0, 0, {}, {}, {}, SERIAL_IO_MEM, NULL }, \ - /* ttyS1 */ \ - { 0, BASE_BAUD, 0, PPC405GP_UART1_INT, STD_COM_FLAGS, 0, 0, 0, 0, 0, 0, 0, \ - PPC405GP_UART1_IO_BASE, 0, 0, 0, {}, {}, {}, SERIAL_IO_MEM, NULL }, - -#endif - - -#define SERIAL_PORT_DFNS \ - STD_SERIAL_PORT_DFNS \ - {} - - - -#endif /* __ASMPPC_PPC4xx_SERIAL_H */ -#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/ppc_asm.h cset-v2.4.20/include/asm-ppc/ppc_asm.h --- cset-v2.4.20~/include/asm-ppc/ppc_asm.h 2004-10-25 14:59:39.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/ppc_asm.h 2004-11-02 17:43:49.000000000 +0900 @@ -115,6 +115,12 @@ bdnz 0b #endif +#ifdef CONFIG_BOOKE +#define tophys(rd,rs) \ + mr rd,rs +#define tovirt(rd,rs) \ + mr rd,rs +#else /* CONFIG_BOOKE */ /* * On APUS (Amiga PowerPC cpu upgrade board), we don't know the * physical base address of RAM at compile time. @@ -132,6 +138,7 @@ .align 1; \ .long 0b; \ .previous +#endif /* CONFIG_BOOKE */ /* * On 64-bit cpus, we use the rfid instruction instead of rfi, but @@ -150,11 +157,17 @@ #else #define FIX_SRR1(ra, rb) +#ifndef CONFIG_4xx #define RFI rfi +#else +#define RFI rfi; b . /* prevent prefetch past rfi */ +#endif #define MTMSRD(r) mtmsr r #define CLR_TOP32(r) #endif /* CONFIG_PPC64BRIDGE */ +#define RFMCI .long 0x4c00004c /* rfmci instruction */ + /* The boring bits... */ /* Condition Register Bit Fields */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/processor.h cset-v2.4.20/include/asm-ppc/processor.h --- cset-v2.4.20~/include/asm-ppc/processor.h 2004-10-25 14:58:44.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/processor.h 2004-11-02 17:38:17.000000000 +0900 @@ -6,6 +6,12 @@ #define __ASM_PPC_PROCESSOR_H /* + * The Book E definitions are hacked into here for 44x right + * now. This whole thing needs regorganized (maybe per-core + * files) * so that it becomes readable. -Matt + */ + +/* * Default implementation of macro that returns current * instruction pointer ("program counter"). */ @@ -47,6 +53,11 @@ #define MSR_RI (1<<1) /* Recoverable Exception */ #define MSR_LE (1<<0) /* Little Endian */ +#ifdef CONFIG_BOOKE +#define MSR_IS MSR_IR /* Instruction Space */ +#define MSR_DS MSR_DR /* Data Space */ +#endif + #ifdef CONFIG_APUS_FAST_EXCEPT #define MSR_ MSR_ME|MSR_IP|MSR_RI #else @@ -91,8 +102,13 @@ #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ #define SPRN_CTR 0x009 /* Count Register */ #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ +#ifdef CONFIG_BOOKE +#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ +#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ +#else #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ +#endif /* CONFIG_BOOKE */ #define SPRN_DAR 0x013 /* Data Address Register */ #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ @@ -111,7 +127,7 @@ #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ #define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */ -#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ +#define SPRN_DBCR 0x3F2 /* Debug Control Register */ #define DBCR_EDM 0x80000000 #define DBCR_IDM 0x40000000 #define DBCR_RST(x) (((x) & 0x3) << 28) @@ -144,11 +160,44 @@ #define DBCR_SDA 0x00000004 /* Second DAC Enable */ #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ +#ifdef CONFIG_BOOKE +#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ +#else #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ +#endif /* CONFIG_BOOKE */ +#define DBCR0_EDM 0x80000000 /* External Debug Mode */ +#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ +#define DBCR0_RST 0x30000000 /* all the bits in the RST field */ +#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ +#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ +#define DBCR0_RST_CORE 0x10000000 /* Core Reset */ +#define DBCR0_RST_NONE 0x00000000 /* No Reset */ +#define DBCR0_IC 0x08000000 /* Instruction Completion */ +#define DBCR0_BT 0x04000000 /* Branch Taken */ +#define DBCR0_EDE 0x02000000 /* Exception Debug Event */ +#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ +#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ +#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ +#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */ +#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */ +#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */ +#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */ +#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */ +#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */ +#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ +#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ +#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ +#ifdef CONFIG_BOOKE +#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ +#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ +#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ +#define DBSR_TIE 0x01000000 /* Book E Trap Instruction debug Event*/ +#else /* CONFIG_BOOKE */ #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ #define SPRN_DBSR 0x3F0 /* Debug Status Register */ #define DBSR_IC 0x80000000 /* Instruction Completion */ #define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ +#endif /* CONFIG_BOOKE */ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define DCCR_NOCACHE 0 /* Noncacheable */ #define DCCR_CACHE 1 /* Cacheable */ @@ -156,7 +205,11 @@ #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ #define DCWR_COPY 0 /* Copy-back */ #define DCWR_WRITE 1 /* Write-through */ +#ifdef CONFIG_BOOKE +#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ +#else #define SPRN_DEAR 0x3D5 /* Data Error Address Register */ +#endif /* CONFIG_BOOKE */ #define SPRN_DEC 0x016 /* Decrement Register */ #define SPRN_DER 0x095 /* Debug Enable Regsiter */ #define DER_RSTE 0x40000000 /* Reset Interrupt */ @@ -181,7 +234,11 @@ #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ #define SPRN_EAR 0x11A /* External Address Register */ +#ifdef CONFIG_BOOKE +#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ +#else #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ +#endif /* CONFIG_BOOKE */ #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ @@ -229,8 +286,13 @@ #define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */ #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ +#ifdef CONFIG_BOOKE +#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */ +#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */ +#else #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ +#endif /* CONFIG_BOOKE */ #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ @@ -318,8 +380,13 @@ #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ +#ifdef CONFIG_BOOKE +#define SPRN_PID 0x030 /* Book E Process ID */ +#define SPRN_PIR 0x11E /* Book E Processor Identification Register */ +#else #define SPRN_PID 0x3B1 /* Process ID */ #define SPRN_PIR 0x3FF /* Processor Identification Register */ +#endif /* CONFIG_BOOKE */ #define SPRN_PIT 0x3DB /* Programmable Interval Timer */ #define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ @@ -341,15 +408,32 @@ #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 (4xx) */ #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 (4xx) */ #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 (4xx) */ +#define SPRG4R SPRN_SPRG4R /* Book E Supervisor Private Registers */ +#define SPRG5R SPRN_SPRG5R +#define SPRG6R SPRN_SPRG6R +#define SPRG7R SPRN_SPRG7R +#define SPRG4W SPRN_SPRG4W +#define SPRG5W SPRN_SPRG5W +#define SPRG6W SPRN_SPRG6W +#define SPRG7W SPRN_SPRG7W #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ +#define SPRN_SU0R 0x3BC /* "User 0" real mode */ +#define SPRN_TBHI 0x3DC /* Time Base High (4xx) */ +#define SPRN_TBHU 0x3CC /* Time Base High User-mode (4xx) */ +#define SPRN_TBLO 0x3DD /* Time Base Low (4xx) */ +#define SPRN_TBLU 0x3CD /* Time Base Low User-mode (4xx) */ #define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */ #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */ -#define SPRN_TBWL 0x11C /* Time Base Lower Register (supervisor, R/W) */ -#define SPRN_TBWU 0x11D /* Time Base Upper Register (supervisor, R/W) */ +#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */ +#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ +#ifdef CONFIG_BOOKE +#define SPRN_TCR 0x154 /* Book E Timer Control Register */ +#else #define SPRN_TCR 0x3DA /* Timer Control Register */ +#endif /* CONFIG_BOOKE */ #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ #define WP_2_17 0 /* 2^17 clocks */ #define WP_2_21 1 /* 2^21 clocks */ @@ -362,6 +446,7 @@ #define WRC_SYSTEM 3 /* System reset will occur */ #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ +#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */ #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ #define FP_2_9 0 /* 2^9 clocks */ #define FP_2_13 1 /* 2^13 clocks */ @@ -381,7 +466,11 @@ #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ #define THRM3_E (1<<0) +#ifdef CONFIG_BOOKE +#define SPRN_TSR 0x150 /* Book E Timer Status Register */ +#else #define SPRN_TSR 0x3D8 /* Timer Status Register */ +#endif /* CONFIG_BOOKE */ #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ @@ -390,6 +479,7 @@ #define WRS_CHIP 2 /* WDT forced chip reset */ #define WRS_SYSTEM 3 /* WDT forced system reset */ #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ +#define TSR_DIS TSR_PIS /* DEC Interrupt Status */ #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ @@ -402,6 +492,57 @@ #define SPRN_XER 0x001 /* Fixed Point Exception Register */ #define SPRN_ZPR 0x3B0 /* Zone Protection Register */ +/* Book E definitions */ +#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ +#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */ +#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */ +#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ +#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ +#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ +#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ +#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ +#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ +#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ +#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ +#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ +#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ +#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ +#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ +#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ +#define SPRN_DVC1 0x13E /* */ +#define SPRN_DVC2 0x13F /* */ +#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ +#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ +#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ +#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ +#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ +#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ +#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ +#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ +#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ +#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ +#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */ +#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */ +#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */ +#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */ +#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */ +#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ +#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ +#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ +#define SPRN_MCSR 0x23c /* Machine Check Syndrom Register */ +#if defined(CONFIG_440A) +#define MCSR_MCS 0x80000000 /* Machine Check Summary */ +#define MCSR_IB 0x40000000 /* Instruction PLB Error */ +#define MCSR_DRB 0x20000000 /* Data Read PLB Error */ +#define MCSR_DWB 0x10000000 /* Data Write PLB Error */ +#define MCSR_TLBP 0x08000000 /* TLB Parity Error */ +#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ +#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ +#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ +#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ +#endif +#define SPRN_MMUCR 0x3b2 /* MMU Control Register */ + /* Short-hand versions for a number of the above SPRNs */ #define CTR SPRN_CTR /* Counter Register */ @@ -425,6 +566,7 @@ #define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */ #define DCMP SPRN_DCMP /* Data TLB Compare Register */ #define DEC SPRN_DEC /* Decrement Register */ +#define DECAR SPRN_DECAR /* Decrementer Auto Reload Register */ #define DMISS SPRN_DMISS /* Data TLB Miss Register */ #define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ #define EAR SPRN_EAR /* External Address Register */ @@ -457,6 +599,7 @@ #define PVR SPRN_PVR /* Processor Version */ #define RPA SPRN_RPA /* Required Physical Address Register */ #define SDR1 SPRN_SDR1 /* MMU hash base register */ +#define USPRG0 SPRN_USPRG0 #define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ #define SPR1 SPRN_SPRG1 #define SPR2 SPRN_SPRG2 @@ -512,6 +655,10 @@ #define PVR_403GCX 0x00201400 #define PVR_405GP 0x40110000 #define PVR_STB03XXX 0x40310000 +#define PVR_440GP_RB 0x40120440 +#define PVR_440GP_RC1 0x40120481 +#define PVR_440GP_RC2 0x40200481 +#define PVR_440GX_RC1 0x51b21850 #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 @@ -672,6 +819,10 @@ vector128 vscr; /* AltiVec status */ unsigned long vrsave; #endif /* CONFIG_ALTIVEC */ +#if defined(CONFIG_4xx) + /* Saved 4xx debug registers */ + unsigned long dbcr0; +#endif }; #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/ptrace.h cset-v2.4.20/include/asm-ppc/ptrace.h --- cset-v2.4.20~/include/asm-ppc/ptrace.h 2004-10-25 14:58:23.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/ptrace.h 2004-11-01 22:35:11.000000000 +0900 @@ -34,7 +34,7 @@ /* Used on APUS to hold IPL value. */ unsigned long trap; /* Reason for being here */ unsigned long dar; /* Fault registers */ - unsigned long dsisr; + unsigned long dsisr; /* used for ESR on 4xx/Book-E */ unsigned long result; /* Result of a system call */ }; #endif diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/scatterlist.h cset-v2.4.20/include/asm-ppc/scatterlist.h --- cset-v2.4.20~/include/asm-ppc/scatterlist.h 2004-10-25 14:59:19.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/scatterlist.h 2004-11-02 17:40:59.000000000 +0900 @@ -12,9 +12,12 @@ * or NULL for highmem page */ struct page * page; /* Location for highmem page, if any */ unsigned int offset; /* for highmem, page offset */ + unsigned int length; /* length at address or page+offset */ dma_addr_t dma_address; /* phys/bus dma address */ - unsigned int length; /* length */ + unsigned int dma_length; /* number of bytes mapped at dma_address */ + /* Note that if we coalesce multiple scatterlist elements, + dma_length can be different from length */ }; /* @@ -25,7 +28,7 @@ * is 0. */ #define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->length) +#define sg_dma_len(sg) ((sg)->dma_length) #endif /* !(_PPC_SCATTERLIST_H) */ #endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/serial.h cset-v2.4.20/include/asm-ppc/serial.h --- cset-v2.4.20~/include/asm-ppc/serial.h 2004-10-25 15:06:25.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/serial.h 2004-11-02 17:41:11.000000000 +0900 @@ -16,127 +16,20 @@ #elif defined(CONFIG_SPRUCE) #include #elif defined(CONFIG_4xx) -#include +#include #else /* - * This assumes you have a 1.8432 MHz clock for your UART. - * - * It'd be nice if someone built a serial card with a 24.576 MHz - * clock, since the 16550A is capable of handling a top speed of 1.5 - * megabits/second; but this requires the faster clock. + * XXX Assume for now it has PC-style ISA serial ports. + * This is true for PReP and CHRP at least. */ -#define BASE_BAUD ( 1843200 / 16 ) +#include +#include -#ifdef CONFIG_SERIAL_MANY_PORTS -#define RS_TABLE_SIZE 64 -#else -#define RS_TABLE_SIZE 4 -#endif - -/* Standard COM flags (except for COM4, because of the 8514 problem) */ -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) -#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF -#endif - -#ifdef CONFIG_SERIAL_MANY_PORTS -#define FOURPORT_FLAGS ASYNC_FOURPORT -#define ACCENT_FLAGS 0 -#define BOCA_FLAGS 0 -#define HUB6_FLAGS 0 +#if defined(CONFIG_MAC_SERIAL) +#define SERIAL_DEV_OFFSET ((_machine == _MACH_prep || _machine == _MACH_chrp) ? 0 : 2) #endif -/* - * The following define the access methods for the HUB6 card. All - * access is through two ports for all 24 possible chips. The card is - * selected through the high 2 bits, the port on that card with the - * "middle" 3 bits, and the register on that port with the bottom - * 3 bits. - * - * While the access port and interrupt is configurable, the default - * port locations are 0x302 for the port control register, and 0x303 - * for the data read/write register. Normally, the interrupt is at irq3 - * but can be anything from 3 to 7 inclusive. Note that using 3 will - * require disabling com2. - */ - -#define C_P(card,port) (((card)<<6|(port)<<3) + 1) - -#define STD_SERIAL_PORT_DEFNS \ - /* UART CLK PORT IRQ FLAGS */ \ - { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ - { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ - { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ - { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ - - -#ifdef CONFIG_SERIAL_MANY_PORTS -#define EXTRA_SERIAL_PORT_DEFNS \ - { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \ - { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \ - { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \ - { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \ - { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \ - { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \ - { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \ - { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \ - { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \ - { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \ - { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \ - { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \ - { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \ - { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \ - { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \ - { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \ - { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \ - { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \ - { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \ - { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \ - { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \ - { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \ - { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \ - { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \ - { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \ - { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \ - { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \ - { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */ -#else -#define EXTRA_SERIAL_PORT_DEFNS -#endif - -/* You can have up to four HUB6's in the system, but I've only - * included two cards here for a total of twelve ports. - */ -#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS)) -#define HUB6_SERIAL_PORT_DFNS \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */ -#else -#define HUB6_SERIAL_PORT_DFNS -#endif - -#define MCA_SERIAL_PORT_DFNS - -#define SERIAL_PORT_DFNS \ - STD_SERIAL_PORT_DEFNS \ - EXTRA_SERIAL_PORT_DEFNS \ - HUB6_SERIAL_PORT_DFNS \ - MCA_SERIAL_PORT_DFNS - #endif /* !CONFIG_GEMINI and others */ #endif /* __ASM_SERIAL_H__ */ #endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/time.h cset-v2.4.20/include/asm-ppc/time.h --- cset-v2.4.20~/include/asm-ppc/time.h 2004-10-25 14:59:25.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/time.h 2004-11-02 17:44:02.000000000 +0900 @@ -32,14 +32,14 @@ int via_calibrate_decr(void); /* Accessor functions for the decrementer register. - * The 4xx doesn't even have a decrementer. I tried to use the - * generic timer interrupt code, which seems OK, with the 4xx PIT + * The 40x doesn't even have a decrementer. I tried to use the + * generic timer interrupt code, which seems OK, with the 40x PIT * in auto-reload mode. The problem is PIT stops counting when it * hits zero. If it would wrap, we could use it just like a decrementer. */ static __inline__ unsigned int get_dec(void) { -#if defined(CONFIG_4xx) +#if defined(CONFIG_40x) return (mfspr(SPRN_PIT)); #else return (mfspr(SPRN_DEC)); @@ -48,7 +48,7 @@ static __inline__ void set_dec(unsigned int val) { -#if defined(CONFIG_4xx) +#if defined(CONFIG_40x) return; /* Have to let it auto-reload */ #elif defined(CONFIG_8xx_CPU6) set_dec_cpu6(val); diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/unistd.h cset-v2.4.20/include/asm-ppc/unistd.h --- cset-v2.4.20~/include/asm-ppc/unistd.h 2004-10-25 15:00:54.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/unistd.h 2004-11-01 22:35:11.000000000 +0900 @@ -244,173 +244,102 @@ #define __NR(n) #n +/* On powerpc a system call basically clobbers the same registers like a + * function call, with the exception of LR (which is needed for the + * "sc; bnslr" sequence) and CR (where only CR0.SO is clobbered to signal + * an error return status). + */ -#define __syscall_return(type) \ - return (__sc_err & 0x10000000 ? errno = __sc_ret, __sc_ret = -1 : 0), \ - (type) __sc_ret - -#define __syscall_clobbers \ - "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12" - -#define _syscall0(type,name) \ -type name(void) \ -{ \ +#define __syscall_nr(nr, type, name, args...) \ unsigned long __sc_ret, __sc_err; \ { \ register unsigned long __sc_0 __asm__ ("r0"); \ register unsigned long __sc_3 __asm__ ("r3"); \ + register unsigned long __sc_4 __asm__ ("r4"); \ + register unsigned long __sc_5 __asm__ ("r5"); \ + register unsigned long __sc_6 __asm__ ("r6"); \ + register unsigned long __sc_7 __asm__ ("r7"); \ \ - __sc_0 = __NR_##name; \ + __sc_loadargs_##nr(name, args); \ __asm__ __volatile__ \ ("sc \n\t" \ - "mfcr %1 " \ - : "=&r" (__sc_3), "=&r" (__sc_0) \ - : "0" (__sc_3), "1" (__sc_0) \ - : __syscall_clobbers); \ + "mfcr %0 " \ + : "=&r" (__sc_0), \ + "=&r" (__sc_3), "=&r" (__sc_4), \ + "=&r" (__sc_5), "=&r" (__sc_6), \ + "=&r" (__sc_7) \ + : __sc_asm_input_##nr \ + : "cr0", "ctr", "memory", \ + "r8", "r9", "r10","r11", "r12"); \ __sc_ret = __sc_3; \ __sc_err = __sc_0; \ } \ - __syscall_return (type); \ + if (__sc_err & 0x10000000) \ + { \ + errno = __sc_ret; \ + __sc_ret = -1; \ + } \ + return (type) __sc_ret + +#define __sc_loadargs_0(name, dummy...) \ + __sc_0 = __NR_##name +#define __sc_loadargs_1(name, arg1) \ + __sc_loadargs_0(name); \ + __sc_3 = (unsigned long) (arg1) +#define __sc_loadargs_2(name, arg1, arg2) \ + __sc_loadargs_1(name, arg1); \ + __sc_4 = (unsigned long) (arg2) +#define __sc_loadargs_3(name, arg1, arg2, arg3) \ + __sc_loadargs_2(name, arg1, arg2); \ + __sc_5 = (unsigned long) (arg3) +#define __sc_loadargs_4(name, arg1, arg2, arg3, arg4) \ + __sc_loadargs_3(name, arg1, arg2, arg3); \ + __sc_6 = (unsigned long) (arg4) +#define __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5) \ + __sc_loadargs_4(name, arg1, arg2, arg3, arg4); \ + __sc_7 = (unsigned long) (arg5) + +#define __sc_asm_input_0 "0" (__sc_0) +#define __sc_asm_input_1 __sc_asm_input_0, "1" (__sc_3) +#define __sc_asm_input_2 __sc_asm_input_1, "2" (__sc_4) +#define __sc_asm_input_3 __sc_asm_input_2, "3" (__sc_5) +#define __sc_asm_input_4 __sc_asm_input_3, "4" (__sc_6) +#define __sc_asm_input_5 __sc_asm_input_4, "5" (__sc_7) + +#define _syscall0(type,name) \ +type name(void) \ +{ \ + __syscall_nr(0, type, name); \ } #define _syscall1(type,name,type1,arg1) \ type name(type1 arg1) \ { \ - unsigned long __sc_ret, __sc_err; \ - { \ - register unsigned long __sc_0 __asm__ ("r0"); \ - register unsigned long __sc_3 __asm__ ("r3"); \ - \ - __sc_3 = (unsigned long) (arg1); \ - __sc_0 = __NR_##name; \ - __asm__ __volatile__ \ - ("sc \n\t" \ - "mfcr %1 " \ - : "=&r" (__sc_3), "=&r" (__sc_0) \ - : "0" (__sc_3), "1" (__sc_0) \ - : __syscall_clobbers); \ - __sc_ret = __sc_3; \ - __sc_err = __sc_0; \ - } \ - __syscall_return (type); \ + __syscall_nr(1, type, name, arg1); \ } #define _syscall2(type,name,type1,arg1,type2,arg2) \ type name(type1 arg1, type2 arg2) \ { \ - unsigned long __sc_ret, __sc_err; \ - { \ - register unsigned long __sc_0 __asm__ ("r0"); \ - register unsigned long __sc_3 __asm__ ("r3"); \ - register unsigned long __sc_4 __asm__ ("r4"); \ - \ - __sc_3 = (unsigned long) (arg1); \ - __sc_4 = (unsigned long) (arg2); \ - __sc_0 = __NR_##name; \ - __asm__ __volatile__ \ - ("sc \n\t" \ - "mfcr %1 " \ - : "=&r" (__sc_3), "=&r" (__sc_0) \ - : "0" (__sc_3), "1" (__sc_0), \ - "r" (__sc_4) \ - : __syscall_clobbers); \ - __sc_ret = __sc_3; \ - __sc_err = __sc_0; \ - } \ - __syscall_return (type); \ + __syscall_nr(2, type, name, arg1, arg2); \ } #define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ type name(type1 arg1, type2 arg2, type3 arg3) \ { \ - unsigned long __sc_ret, __sc_err; \ - { \ - register unsigned long __sc_0 __asm__ ("r0"); \ - register unsigned long __sc_3 __asm__ ("r3"); \ - register unsigned long __sc_4 __asm__ ("r4"); \ - register unsigned long __sc_5 __asm__ ("r5"); \ - \ - __sc_3 = (unsigned long) (arg1); \ - __sc_4 = (unsigned long) (arg2); \ - __sc_5 = (unsigned long) (arg3); \ - __sc_0 = __NR_##name; \ - __asm__ __volatile__ \ - ("sc \n\t" \ - "mfcr %1 " \ - : "=&r" (__sc_3), "=&r" (__sc_0) \ - : "0" (__sc_3), "1" (__sc_0), \ - "r" (__sc_4), \ - "r" (__sc_5) \ - : __syscall_clobbers); \ - __sc_ret = __sc_3; \ - __sc_err = __sc_0; \ - } \ - __syscall_return (type); \ + __syscall_nr(3, type, name, arg1, arg2, arg3); \ } #define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ { \ - unsigned long __sc_ret, __sc_err; \ - { \ - register unsigned long __sc_0 __asm__ ("r0"); \ - register unsigned long __sc_3 __asm__ ("r3"); \ - register unsigned long __sc_4 __asm__ ("r4"); \ - register unsigned long __sc_5 __asm__ ("r5"); \ - register unsigned long __sc_6 __asm__ ("r6"); \ - \ - __sc_3 = (unsigned long) (arg1); \ - __sc_4 = (unsigned long) (arg2); \ - __sc_5 = (unsigned long) (arg3); \ - __sc_6 = (unsigned long) (arg4); \ - __sc_0 = __NR_##name; \ - __asm__ __volatile__ \ - ("sc \n\t" \ - "mfcr %1 " \ - : "=&r" (__sc_3), "=&r" (__sc_0) \ - : "0" (__sc_3), "1" (__sc_0), \ - "r" (__sc_4), \ - "r" (__sc_5), \ - "r" (__sc_6) \ - : __syscall_clobbers); \ - __sc_ret = __sc_3; \ - __sc_err = __sc_0; \ - } \ - __syscall_return (type); \ + __syscall_nr(4, type, name, arg1, arg2, arg3, arg4); \ } #define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \ { \ - unsigned long __sc_ret, __sc_err; \ - { \ - register unsigned long __sc_0 __asm__ ("r0"); \ - register unsigned long __sc_3 __asm__ ("r3"); \ - register unsigned long __sc_4 __asm__ ("r4"); \ - register unsigned long __sc_5 __asm__ ("r5"); \ - register unsigned long __sc_6 __asm__ ("r6"); \ - register unsigned long __sc_7 __asm__ ("r7"); \ - \ - __sc_3 = (unsigned long) (arg1); \ - __sc_4 = (unsigned long) (arg2); \ - __sc_5 = (unsigned long) (arg3); \ - __sc_6 = (unsigned long) (arg4); \ - __sc_7 = (unsigned long) (arg5); \ - __sc_0 = __NR_##name; \ - __asm__ __volatile__ \ - ("sc \n\t" \ - "mfcr %1 " \ - : "=&r" (__sc_3), "=&r" (__sc_0) \ - : "0" (__sc_3), "1" (__sc_0), \ - "r" (__sc_4), \ - "r" (__sc_5), \ - "r" (__sc_6), \ - "r" (__sc_7) \ - : __syscall_clobbers); \ - __sc_ret = __sc_3; \ - __sc_err = __sc_0; \ - } \ - __syscall_return (type); \ + __syscall_nr(5, type, name, arg1, arg2, arg3, arg4, arg5); \ } diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/include/asm-ppc/walnut.h cset-v2.4.20/include/asm-ppc/walnut.h --- cset-v2.4.20~/include/asm-ppc/walnut.h 2004-10-25 15:04:11.000000000 +0900 +++ cset-v2.4.20/include/asm-ppc/walnut.h 2004-11-01 22:35:11.000000000 +0900 @@ -1,58 +1,3 @@ /* * BK Id: SCCS/s.walnut.h 1.10 09/14/01 17:37:56 trini */ -/* - * - * Copyright (c) 1999 Grant Erickson - * - * Copyright 2000 MontaVista Software Inc. - * PPC405 modifications - * Author: MontaVista Software, Inc. - * frank_rowand@mvista.com or source@mvista.com - * debbie_chu@mvista.com - * - * Module name: ppc405.h - * - * Description: - * Macros, definitions, and data structures specific to the IBM PowerPC - * based boards. - * - * This includes: - * - * 405GP "Walnut" evaluation board - * - */ - -#ifdef __KERNEL__ -#ifndef __WALNUT_H__ -#define __WALNUT_H__ - -#ifndef __ASSEMBLY__ -/* - * Data structure defining board information maintained by the boot - * ROM on IBM's "Walnut" evaluation board. An effort has been made to - * keep the field names consistent with the 8xx 'bd_t' board info - * structures. - */ - -typedef struct board_info { - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[30]; /* Version of the IBM ROM */ - unsigned int bi_memsize; /* DRAM installed, in bytes */ - unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */ - unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ - unsigned int bi_procfreq; /* Processor speed, in Hz */ - unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ - unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ -} bd_t; - -#endif /* !__ASSEMBLY__ */ - -/* Memory map for the IBM "Walnut" 405GP evaluation board. - * Generic 4xx plus RTC. - */ -#define WALNUT_RTC_ADDR ((uint)0xf0001000) -#define WALNUT_RTC_SIZE ((uint)4*1024) - -#endif /* __WALNUT_H__ */ -#endif /* __KERNEL__ */ diff -X /home/doyu/.dontdiff -uNrbBw cset-v2.4.20~/net/core/rtnetlink.c cset-v2.4.20/net/core/rtnetlink.c --- cset-v2.4.20~/net/core/rtnetlink.c 2004-10-25 15:04:46.000000000 +0900 +++ cset-v2.4.20/net/core/rtnetlink.c 2004-11-01 22:35:11.000000000 +0900 @@ -394,7 +394,7 @@ * Malformed skbs with wrong lengths of messages are discarded silently. */ -extern __inline__ int rtnetlink_rcv_skb(struct sk_buff *skb) +__inline__ int rtnetlink_rcv_skb(struct sk_buff *skb) { int err; struct nlmsghdr * nlh;